Apostolos Dollas

Predicting and precluding problems with memory latency

By examining the rate at which successive generations of processor and DRAM cycle times have been diverging over time, we can track the latency problem of computer memory systems. Our research survey starts with the fundamentals of single-level caches and moves to the need for multilevel cache hierarchies. We look at some of the current techniques for boosting cache performance, especially compiler-based methods for code restructuring and instruction and data prefetching. These two areas will likely yield improvements for a much larger domain of applications in the future.<<ETX>>

An open TCP/IP core for reconfigurable logic

This project is aimed at developing the full TCP/IP protocol as an open-source IP core which can be freely used, as well as to develop know-how on protocol boosting for complex protocols such as TCP/IP. The problem was quite challenging, especially if we consider that just about all commercial implementations of TCP/IP do not fully implement all of the protocol specifications.

The evolution of instruction sequencing

The three distinct phases that constitute the sequencing of an instruction are determining the memory address that contains the instruction, fetching the instruction from memory, and executing the instruction. The evolution of instruction sequencing is traced, with attention focused on the influence of the available technology on the minimum time required for each of these phases and the resulting design decisions. Rather than absolute system performance. the interrelationship of these critical parameters is examined. Memory bandwidth, instruction buffers, caches, and the impact of reduced-instruction-set computers (RISCs) are discussed. Recent innovations are described, and the options and constraints that designers face with respect to future developments are evaluated.<<ETX>>

FPGA Based Low Cost Generic Reusable Module for the Rapid Prototyping of Subsystems

The development of a model for sub-system reuse and the evaluation of currently available rapid prototyping platforms has led to the development of a GEneric Reusable Module (GERM). The GERM is a low-cost, stand-alone, reprogrammable development tool designed for prototyping digital subsystems. The GERM, and associated templates, aid the designer in rapidly prototyping and reusing subsystem designs. The GERM addresses also the introduction of students to FPGA technology in an environment which they can continue to use for more complex designs. Extensions of the GERM include combining multiple GERMs together to prototype larger subsystems and systems. The system was used successfully in computer engineering courses at Duke University.

Experimental results in rapid system prototyping with incomplete CAD tools and inexperienced designers

The effect of designer inexperience and incomplete CAD tool suites on the rapid prototyping of microelectronic systems was studied through a course on advanced digital system design. Some of the results confirm that well known and respected design methodologies are indeed preferable to other alternatives, whereas other results showed previously unknown traits. All of the projects were successfully completed, demonstrating that the stated limitations can be overcome. The results of the study are discussed.<<ETX>>

Extended VHDL for the rapid prototyping of systems with synthesizable and nonsynthesizable subsystems

System design is typically done in VHDL to facilitate top-down design and to enable the mapping of a design to many implementations. Reusability of subsystems to date has largely been performed with libraries of synthesizable VHDL subsystems. This paper presents recommended extensions to VHDL to allow the VHDL designer to interact with nonsynthesizable subsystems while still designing in VHDL. The extended VHDL code is passed through a precompiler that outputs two standard VHDL files: a simulatable VHDL model of the system, and a synthesizable model of the design where subsystems are replaced by signals to the external hardware.<<ETX>>

Rapid Prototyping of Microelectronic Systems

Abstract The need for reduced time to market of new designs has mandated the development of a new generation of computer-aided design tools and design methodologies. The active pursuit of a substantial time reduction in the design process is encompassed in rapid system prototyping. This chapter introduces the field and the disciplines it comprises, and presents extensive examples of research activities in many key disciplines. New technologies, such as field programmable gate arrays, and new methodologies, such as subsystem reusability, are presented. The directions in formalizing the process of system design from specifications through delivery of a functional system are also discussed.

An interactive environment for the transparent logic simulation and testing of integrated circuits

An interactive environment utilizing a knowledge-based system for the transparent testing of integrated circuits from simulation data has been developed. Unique features of this system are its modularity and its ease of expansion with new simulators and testers. The system uses the Omnitest language and a tester description language. The environment is fully operational and has been used to test several fabricated integrated circuits. An example illustrating the operation of the system is presented.<<ETX>>

A knowledge-based environment for the integration of logical and physical testing of VLSI circuits

The authors have developed an application environment for VLSI design, under which the VLSI design tools as well as the testers can be run. They have also developed a knowledge-based system for the transparent use of various testers from a common intermediate test-pattern language. Under the new environment, the user stimulates a design as before, and then specifies on which tester the fabricated design should be tested. The tests are performed with minimal user intervention (e.g. powering the circuit up). Upon completion of the physical testing the system compares the test data to the simulation data and graphically presents discrepancies which may indicate potential errors.<<ETX>>

Nonparametric graded data processing with back-error propagation networks

Abstract We present some computational characteristics of back-error propagation (BEP) networks in processing graded patterns that are otherwise indistinguishable in binary (or bipolar) representations. We address the problem of mapping l-of-m unit gradients with interunit activation profile d to n classes, where maximum noise amplitude of ϵ is permitted within gradient classes. Relations between these parameters and the training period measured in epochs (T) are discussed. Extensions of basic concepts are used to extract embedded feature information in constrained 2D grey-scale patterns and to group and classify distorted pattern clusters whose intraset distances are sometimes greater than interset metrics. Results have been applied to simulation studies in the domain of robotic tactile pattern recognition.