Arne Heittmann

Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits

In this paper, limits of writing multivalued resistances in passive nanoelectronic crossbars are examined. The results are based on circuit simulation including device models for resistive switches based on the electrochemical metallization effect. The write operation is performed using a current mirror based on 40nm CMOS technology which operates in subthreshold mode. The results show that only sparsely coded pattern with low mutual overlap can be robustly brought into the matrix which limits the use of passive crossbar to applications that feature particular spatial distributions of resistive weights.

A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars

The performance of a method for robustly writing conductive states into resistive switches is analyzed. The focus is set on the variability of the conductance distribution which has a strong impact on the signal margin and the robustness of the circuit performance. In order to be able to capture cycle-to-cycle as well as device-to-device variability an existing device model for ECM cells was extended and prepared to be executable on standard circuit simulation platforms. The ECM devices were embedded into a passive crossbar whereby electrical worst case conditions were identified by Monte Carlo simulations. Under the constraint of specified signal margins to be maintained for the read operation the underlying write circuit was optimized.

Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization

This paper describes a neuromorphic circuit based on resistive switches arranged in a crossbar architecture. Using pulses as general signal representation the circuit in particular is sensitive to the degree of synchronization of the input pulses. In order to examine different effects of pulse synchronization on the input/output characteristics of the circuit, an architecture for the implementation of a filter is presented which is selective to oriented edges and lines. By theoretical analysis as well as simulative verification effects of attenuation and distortion are described which are related to statistical properties of input pulses. The results prepare the ground for new signal processing schemes in pulse coded neural networks.

PTM-based V T -variability analysis and compensation of a nanoscaled comparator circuit based on finfets and resistive switches

The impact of process variability on the performance of an unbuffered nanoscaled comparator applied to hybrid nanoelectronic crossbar memory circuits is analyzed. The analysis is done for circuits based on tri-gate (TG) FinFets for 16nm, 14nm, 10nm, and 7nm technology nodes. Monte-Carlo simulations were carried out based on predictive technology models (PTM) incorporating models for metal gate granularity (MGG), line edge roughness (LER) for transistor length and fin width. The results show that the spread of the amplifiers trigger voltage can be larger than 200mV. A static VT-offset cancelation scheme exploiting the multilevel capabilities of resistive switches is proposed and statistically analyzed. The results show that the VT-variability can be reduced below 10mV by using the proposed RS-based reference circuits.

Variability analysis of a hybrid CMOS/RS nanoelectronic calibration circuit

In this paper, a novel adaptable reference circuit is proposed which can be used to calibrate the switching threshold of a read amplifier. The circuit is based on a network of nanoelectronic resistive switches acting as voltage dividers. In addition, active CMOS circuits are included which are used to tune the output voltage of the circuit. For the performance analysis variability models were applied for both, the CMOS part as well as the resistive switch part. The analysis shows that the output voltage can achieve a resolution for the reference voltage considerably better than 5mV. Finally, the tradeoff between resolution and required programming time is elaborated.

Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits

One significant challenge in the design of nanoelectronic circuits which comprise resistive switches (RS) beyond 10 nm feature size is to control the variability and the irreproducibility of RS device conductance. For RS, which are based on the electrochemical metallization effect (ECM), this variability is - amongst others - caused by random discrete electrochemical reactions during the filament growth. Based on a physical model for ECM cells a 1D Monte Carlo circuit simulation model was derived which models the occurrence of individual electrochemical reactions by a Poisson process. By circuit simulation it was possible to show that the conductance variation during the filament growth can be controlled by a regulating device, which establishes a negative feedback on the electrochemical reaction rate. In particular, for three different load types (current source, linear resistor, and source coupled NMOS transistor) the regulating properties in regard to variability reduction (and partly observed in experiments) were shown by Monte Carlo simulation. It was especially possible to show that the obtained conductance variation appears to be the consequence of the respective dynamic joint interaction between RS and the regulating device and is -in turn- not a predetermined property of the RS alone.

Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays

In this paper, an area-delay metric (AT) of hybrid memristive/CMOS memory architectures is discussed. The proposed memory circuit can be used as a lookup table in field programmable gate arrays (FPGAs) and is modeled by a passive nanoelectronic crossbar comprising resistive switches (RS) as memory elements. In particular, resistive switches which are based on the electrochemical metallization effect (ECM) are assumed. At the periphery, CMOS circuits are included with provide appropriate voltage levels for robust read and write operations. The optimization of the CMOS periphery was done for a 40-nm CMOS technology, and especially in regard to the physical properties of ECM cells which allows for the derivation of a realistic AT metric for the memory core circuit. For different architectural choices, the evaluation of the AT metric shows, that the area overhead which is caused by the peripheral CMOS circuits significantly determines the total circuit area. Under almost all conditions the required silicon area per bit is far beyond 4F2 (F: lithographic resolution), but for particular conditions the effective area per bit is smaller than the area per bit which is required for a corresponding SRAM core circuit.

Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation

This paper presents a device model for nanoelectronic resistive switches which are based on the electrochemical metallization effect (ECM). The focus is set on modeling variability as well as irreproducibility which are essential properties of scaled nanoelectronic devices. In particular, a Poisson-based random ion deposition model and a non-linear filament surface effect are described. The model is especially useful for circuit simulation and can be implemented on standard circuit simulation platforms such as Spice or Spectre using inbuilt standard elements. Based on this model, effects of variability were examined by Monte Carlo simulation for a particular hybrid CMOS/nanoelectronic circuit. The results show that the proposed model is able to cover significant scaling effects, which is necessary for prospective design space exploration and circuit optimization.

Monte Carlo simulation of multilevel switching in hybrid CMOS/memristive nanoelectronic circuits

Conductance variations in nanoelectronic resistive switches seriously affect the performance of hybrid CMOS/memristive circuits. In order to capture cycle-to-cycle variability by circuit simulation a standard model was extended for resistive switches based on the electrochemical metallization effect. The extension incorporates an additional process that simulates the randomness of the filament growth and is prepared to be executable on standard circuit simulation platforms. The results show that the randomness of filament growth significantly affects the conductance variations and needs to be considered for circuit simulation of scaled devices.

Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells

A neuromorphic architecture based on Binary Associative memories and nanoelectronic resistive switches is proposed for the realization of arbitrary logic/arithmetic functions. Subsets of non-trivial code sets based on error detecting 2-out-of-n-codes are thoroughly used to encode operands, results, and intermediate states in order to enhance the circuit reliability by mitigating the impact of device variability. 2-ary functions can be implemented by cascading a mixer memory, a correlator memory, and a response memory. By introduction of a new cost function based on class-specific word-line-coverage, stochastic optimization is applied with the aim to minimize the overall number of active amplifiers. For various exemplary functions optimized architectures are compared against solutions obtained using a standard-cost function. It is especially shown that the consideration of word-line-coverage results in a significant circuit compaction.