Arnold M. Frisch

Timing analyzer for embedded testing

A 20 channel timing analyzer was designed in CMOS for embedded testing applications. The chip executes independent events in each of the channels at rates of 100 MHz, with a precision of 312.5 ps. The chip automatically adjusts for clock rates from 10 to 100 MHz and temperature/process variations, and can be calibrated to compensate for clock skew.<<ETX>>

HABIST: histogram-based analog built in self test

This histogram based method of test collects a statistical representation of the activity at a node and processes that representation using a template histogram as a reference. In most cases, no special stimulus is required-data is collected in-situ, while the circuit under test is functioning. (Alternatively, analog stimulus, e.g. using a pseudo random sequence generator or stored digital vectors with a D to A converter, may be provided). The result of processing the data against the template histogram is a compressed human readable signature that defines gain, offset, noise, and distortion errors. These errors can then be used heuristically to determine causation. This paper describes the HABIST method and optional variations in its implementation, algorithms for processing histograms to obtain signatures and other compressed form of data, including waveform parameters, examples of the difference histograms that result from applying the algorithm, and methods and circuits for histogram generation.

Supplying known good die for MCM applications using low cost embedded testing

A ready supply of high quality Known Good Die (KGD) is essential for obtaining acceptable Multi-Chip Module (MCM) yields and reducing costs. Unfortunately, the testers needed for testing and screening VLSI chips to supply high quality KGD are quite expensive, especially for high speed or high pin count ICs. In addition, there are issues connected with testing accuracy-the tester environment may limit performance testing because of interconnect length and capacitance, and with burn-in-which may require temporary packaging of die. Building special test equipment is only cost effective if production volumes are large. Hence, a low cost alternative for at-speed testing that yields high quality die is needed to drive down the cost of low volume or prototype MCMs. This paper describes a double-blind experiment devised to prove the viability of a KGD methodology based upon wafer level test-using embedded performance testing circuits-and wafer level burn-in.

A/MS BISTs: the facts, just the facts

There have been a great number of different research efforts into the area of analog and mixed signal BIST. And most efforts appear to be very insular -they are the efforts of a single entity. Seldom does another research entity follow up on the research of another. Thats because there is little credit involved in proving someone else is right. And for competitive reasons, and because of patent protection, this extends to commercial BIST providers also. Analog and mixed-signal BIST is alive, well, and here now. It works and it saves time and money.