Arnold Weinberger

High Speed Decimal Addition

Parallel decimal arithmetic capability is becoming increasingly attractive with new applications of computers in a multi-programming environment. The direct production of decimal sums offers a significant improvement in addition over methods requiring decimal correction. These techniques are illustrated in the eight-digit adder which appears in the System/360 Model 195.

High-speed programmable logic array adders

Programmable Logic Array (PLA) adders are described which perform an addition in one cycle with a single pass through a PLA and require a reasonable number of product terms for an 8-, 16-, or even a 32-bit adder. The PLA features two-bit input decoders feeding an AND array followed by an OR array whose outputs are pairwise Exclusive-ORed. Carry-look-ahead adder equations, adapted to the PLA to require relatively few product terms, are adjusted for maximum sharing of product terms. The number of unique product terms is a relative measure of one of the physical dimensions of the PLA. Equations for contiguous sum bits are grouped into strings, each using a common input carry. A procedure optimally assigns sum bits to strings to further minimize the total number of unique product terms. The methods are extended to PLAs with decoders of increased inputs and substantially reduced product terms. They can serve as dedicated macro functions on a chip, using special decoders relevant to adders. As a result, the other PLA dimension comprising the number of outputs from all input decoders increases only moderately, and can even decrease, with larger decoders. Finally, the PLA adder can be further substantially compressed by splitting the OR array into two parts such that a row of the AND array is shared between two product terms, and an OR array column is shared between two sums of product terms.

High-speed zero-sum detection

A common requirement accompanying high-speed parallel addition is the early detection that the sum is equal to zero. Normally, this condition is detected from the sum, generally at least two logic gate levels after the sum.

Using Digital Computers in the Design and Maintenance of New Computers

To conserve manpower and reduce the time needed for designing, assembling, and maintaining new large-scale computers, existing computers have been used to produce design and maintenance data for the new machines automatically. This paper describes some techniques that were devised at the National Bureau of Standards for automatically converting a logical design into detailed wiring plans which specify the actual pin-to-pin connections and other data necessary for assembling, debugging, and maintaining a new machine. Starting from punched-card input transcriptions of the logical design of the new computer, expressed in terms of Boolean algebra, an IBM 704 was programmed to produce 20,000 printed pages of wiring plans, fabrication data, and logical debugging and maintenance manuals.

An adder design optimized for DCS logic

The basic DCS logic gate provides a two-way SELECT function and, with modifications, a two-way XOR, OR, or AND function. Furthermore, outputs of DCS gates can be wired together (dotted) to perform dotted SELECT, XOR, OR, or AND functions. The versatility of this logic is illustrated in the design of a carry-lookahead adder.

Parallel adders using standard plas

PLA adders are described that add in one cycle and require a reasonable number of product terms for an 8, 16, or even a 32-bit adder. A procedure is also described for minimizing the number of product terms for any size adder.