Arturo Diaz-Perez

A parallel architecture for fast computation of elliptic curve scalar multiplication over GF(2/sup m/)

Summary form only given. We present a generic parallel architecture for fast elliptic curve scalar multiplication over binary extension fields. We show how the parallel strategy followed in this work leads to high performance designs. We also implemented the proposed architecture on reconfigurable hardware devices where the predicted expeditious performance figures were actually obtained. The results achieved show that our proposed design is able to compute GF(2/sup 191/) elliptic curve scalar multiplication operations in 56.44 /spl mu/Secs.

A fast parallel implementation of elliptic curve point multiplication over GF(2m)

Abstract A fast parallel architecture for the implementation of elliptic curve scalar multiplication over binary fields is presented. The proposed architecture is implemented on a single-chip FPGA device using parallel strategies that trades area requirements for timing performance. The results achieved show that our proposed design is able to compute GF(2191) elliptic curve scalar multiplication operations in 63 μs.

AES algorithm implementation - an efficient approach for sequential and pipeline architectures

We present an efficient implementation of the Rijndael cryptographic algorithm on FPGAs, which is a new advanced encryption standard (AES). The implementation of AES has been carried out in both sequential and pipeline architectures and we are able to compare the results as an area time trade-off. In sequential architecture, the design occupies 2744 CLB slices and achieves a throughput of 258.5 Mbit/s and there is no use of extra memory resources like FPGA BRAMS. On the other hand, our pipeline design occupies a total of 2136 CLB slices and achieved a throughput of 2868 Mbit/s. Both designs were realized on the VirtexE family of devices (XCV812). The performance figures achieved by our implementations are not only efficient in terms of throughput but also areas occupied by them are among the most economical reported to date.

A reconfigurable processor for high speed point multiplication in elliptic curves

This paper presents a generic architecture for the computation of elliptic curve scalar multiplication over binary extension fields. In order to optimise the performance as much as we could, we designed a parallelised version of the well-known Montgomery point multiplication algorithm implemented on a reconfigurable hardware platform (Xilinx XCV3200). The proposed architecture allows the computation of the main building blocks required by the Montgomery algorithm in an efficient manner. The results achieved show that our proposed design is able to compute GF(2191) elliptic curve scalar multiplication operations in just 22 clock cycles at a frequency of about 10 MHz. Moreover, our structure is able to obtain a scalar multiplication in less than 60 µSecs.

A parallel architecture for computing scalar multiplication on Hessian elliptic curves

A parallel architecture for the computation of Hessian elliptic curve scalar multiplication over binary fields is presented. The architecture was designed as general as possible trying to make no assumptions about the specific hardware platform to be used by the designers. The idea of using parallel strategies was considered in every design stage and implemented as much as hardware resources allowed us to do it so. The design results reported allow us to compute GF(2/sup 191/) elliptic curve scalar multiplication operations in about 114.7/spl mu/ Secs.

Correlation analysis of complex network metrics on the topology of the Internet

We present an experimental study on the linear relationship between a rich set of complex network metrics, to methodologically select a subset of non-redundant and potentially independent metrics that explain different aspects of the topology of the Autonomous System view of the Internet. We followed a data-driven approach based on (1) a correlation study of different properties of evolving Internet networks, and (2) the validation of a non-redundant set of metrics by evaluating the performance of supervised and unsupervised machine learning techniques. We confirm pair-wise metric correlations observed in other types of networks and identify sets of highly correlated metrics that may reveal patterns specific to the topology of the Internet.

Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core

In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling processes. High performance timing figures are obtained through the use of a pipelined architecture. Moreover, several modifications to the conventional AES algorithm’s formulations have been introduced, thus allowing us to obtain a significant reduction in the total number of computations and the path delay associated to them. Particularly, for the implementation of the most costly step of AES, multiplicative inverse in GF(28), two approaches were considered. The first approach uses pre-computed values stored in a lookup table giving fast execution times of the algorithm at the price of memory requirements. Our second approach computes multiplicative inverse by using composite field techniques, yielding a reduction in the memory requirements at the cost of an increment in the execution time. The obtained results indicate that both designs are competitive with the fastest complete AES single-chip FGPA core implementations reported to date. Our first approach requires up to 11.8% less CLB slices, 21.5% less BRAMs and yields up to 18.5% higher throughput than the fastest comparable implementation reported in literature.

Scalable GF( p ) Montgomery multiplier based on a digit–digit computation approach

This study presents a scalable hardware architecture for modular multiplication in prime fields GF( p ). A novel iterative digit-digit Montgomery multiplication (IDDMM) algorithm is proposed and two hardware architectures that compute that algorithm are described. The input operands (multiplicand, multiplier and modulus) are represented using as radix β = 2 k . Multiplication over GF( p ) is possible using almost the same hardware since the complexity of multipliers kernel module depends mainly on k and not on p . The novel hardware architectures of GF( p ) multipliers were evaluated on three Xilinx FPGA families. Design trade-offs were analysed considering different operand sizes commonly used in cryptography and different digits sizes. The proposed designs for IDDMM are well suited to be implemented in modern FPGAs, making use of available dedicated multipliers and memory blocks reducing drastically the FPGAs standard logic while keeping an acceptable performance compared with other implementation approaches. From the Virtex5 implementation, the proposed MM multiplier reaches a throughput of 242 Mbps using only 219 FPGA slices and achieving a 1024-bit modular multiplication in 4.21μs. This is 26 times less area resources than similar related works in the literature with an improved efficiency of 7x.

A compact FPGA-based montgomery multiplier over prime fields

This work describes a compact FPGA hardware architecture for computing modular multiplications over GF(p) using the Montgomery method, suitable for public key cryptography for embedded or mobile systems. The multiplier is parameterizable, allowing to evaluate the hardware design for different prime fields using different radix of the form β = 2k. The design uses only three k x k multipliers and three 2k-bit adders. The hardware organization of the multiplier maximizes the use of the multipliers processing iteratively the multiplicand, multiplier and modulus. The parametric design allows to study area-performance trade offs, in order to meet system requirements such as available resources, throughput, and efficiency. The proposed multiplier achieves a 1024-bit modular multiplication in 15.63 μs using k = 32. Compared to the most compact FPGA implementation previously reported, our proposed design uses 79% less FPGA resources with better efficiency expressed as Mbps/Slice.

FedIDS: a federated cloud storage architecture and satellite image delivery service for building dependable geospatial platforms

ABSTRACT Earth observation satellites produce large amounts of images/data that not only must be processed and preserved in reliable geospatial platforms but also efficiently disseminated among partners/researchers for creating derivative products through collaborative workflows. Organizations can face up this challenge in a cost-effective manner by using cloud services. However, outages and violations of integrity/confidentiality associated to this technology could arise. This article presents FedIDS, a suite of cloud-based components for building dependable geospatial platforms. The Fed component enables organizations to build shared geospatial data infrastructure through federation of independent cloud resources to withstand outages, whereas IDS avoids violations of integrity/confidentiality of images/data in sharing information and collaboration workflows. A FedIDS prototype, deployed in Spain and Mexico, was evaluated through a study case based on a satellite imagery captured by a Mexican antenna and another based on a satellite imagery of a European observation mission. The acquisition, storage and sharing of images among users of the federation, the exchange of images between Mexican and Spanish sites and outage scenarios were evaluated. The evaluation revealed the feasibility, reliability and efficiency of FedIDS, in comparison with available solutions, in terms of performance, storage consume and integrity/confidentiality when sharing images/data in collaborative scenarios.