Arturo Fernández

On the Limit of the Output Capacitor Reduction in Power-Factor Correctors by Distorting the Line Input Current

Active power-factor correctors (PFCs) are needed to design ac-dc power supplies with universal input voltage range and sinusoidal input current. The classical method to control PFCs consists in two feedback loops and an analog multiplier. Hence, the input current is sinusoidal and it is in-phase with the input voltage. However, a bulk capacitor is needed to balance the input and the output power. Due to its high capacitance, an electrolytic capacitor is traditionally used as a bulk capacitor in PFCs. As a consequence, the lifetime of the ac-dc power supply is limited by the electrolytic capacitors, which becomes insufficient to some applications (e.g., high-brightness LEDs). This paper proposes a reduction of the output voltage ripple (which allows reduction of the output capacitance) by distorting the input current, but maintaining the harmonic continent compatible with EN 61000-3-2 regulations. The limits of this output capacitor reductions are deduced. Also, a control strategy based on a low-cost microcontroller is developed to put the proposed study into practice. Finally, the theoretical results are validated in a 500-W prototype.

Design-Oriented Analysis and Performance Evaluation of a Low-Cost High-Brightness LED Driver Based on Flyback Power Factor Corrector

This paper presents a new control strategy for power factor correctors (PFCs) used to drive high-brightness light-emitting diodes (HB-LEDs). This control strategy is extremely simple and is based on the use of standard peak-current-mode integrated controllers (PCMICs), reducing its cost and complexity in comparison to traditional PFC controllers. In fact, this method is an alternative implementation of the one-cycle control to PFCs belonging to the flyback family of converters, without introducing high complexity for reducing the total harmonic distortion. In this case, the use of a simple exponential compensation ramp instead of a linear one is the proposed solution for drawing a sinusoidal input current. Moreover, the line current is cycle-by-cycle controlled, and therefore, the input-current feedback loop is extremely fast, which allows the use of this type of control with high-frequency lines. The proposed idea is to apply this simple control to a one-stage PFC in order to design a low-cost ac-dc HB-LED driver. However, the application of this control strategy to PFC belonging to the flyback family of converters is not obvious. Design-oriented considerations about its implementation in PCMIC will be provided. Finally, an experimental prototype of this driver was developed.

EMI Radiated Noise Measurement System Using the Source Reconstruction Technique

One of the requirements that electronics circuits must satisfy comprises conducted and irradiated noise specifications. Whereas conducted noise is well covered in the literature, radiated noise is not. Radiated noise regulations impose limits on the noise measured 3 or 10 m away from electronic equipment. These measurements are usually made in anechoic rooms, which are very expensive. Moreover, the measurement procedure is not a ldquoplug-and-playrdquo feature, but requires a strict measuring protocol. Once the electronic circuit has been tested, the designer remains ignorant of the source of the problem should the regulation not be met. Hence, the procedure to make an electronic circuit comply with regulations is usually one of trial-and-error, in which the experience of the designer is essential. A new radiated noise measurement technique is proposed in this paper with a twofold objective: to simplify the measurement procedure and to obtain more information about noise sources. The main idea is to scan the electric/magnetic field at two arbitrary although known distances. From these measurements, the source reconstruction technique enables the identification of the noise sources in the surface of the circuit and the field estimation at any distance and the assessment of compliance with regulations. Moreover, if regulations are not met, the effect of modifying the noise source can be tested in order to ascertain how the circuit should be modified to comply with regulations.

Helpful hints to select a power-factor-correction solution for low- and medium-power single-phase power supplies

This work presents a review of power-factor-correction (PFC) circuits for low- and medium-power single-phase power supplies. The main idea is not just to show the state of the art of this topic but to select the most interesting topologies for each application depending on the power level, the input voltage range, and the output voltage. Since IEC 61000-3-2 regulations came into force, many new topologies have been presented trying to obtain a cost-effective solution to reduce the input current harmonic content. Each one of them has its application range due to the inherent characteristics of the topology. Obviously, not every converter is useful for the same application. This is especially perceptible in PFC circuits due to the large amount of different solutions. Hence, this paper tries to show the most appropriate topologies for each application, being the input power and the IEC 61000-3-2 Class some of the main parameters to select it. The scope of the paper is focused on single-phase power supplies belonging to IEC 61000-3-2 Class A and Class D with an input power level below 4 kW.

Dynamic limits of a power-factor preregulator

Power-factor correction has been one of the hottest topics during the last few years and, hence, many new circuits have appeared. In general, it is assumed that preregulators based on multiplier circuits have poor dynamics and, then, a second stage is needed to improve the output voltage dynamic behavior. The other option is the use of single-stage topologies which have fast output voltage regulation although the input current waveform is not sinusoidal. This work presents an analysis of the dynamic behavior of a conventional power-factor preregulator. The objective is to find the limits of the dynamic characteristics of these circuits when the priority is to improve the output voltage regulation and not the total harmonic distortion or the power factor. A large-signal model is presented and the theoretical results are validated with a prototype.

Multiple output AC/DC converter with an internal DC UPS

The usual way to avoid a computer shutdown during a mains failure is to connect an ac uninterruptible power system (UPS). However, there are other possibilities, such as using a dc UPS to obtain the dc output voltages directly from the battery instead of generating an ac voltage to feed the whole power supply. Thus, the topology must operate either from the ac mains or from a battery. A complete design of an ac/dc power supply with an internal dc UPS is presented in this paper. The solution is based on the coupling of the UPS to the main transformer. Moreover, the power supply meets all the requirements needed to be used as an Advanced Technology eXtended (ATX) PC power supply-multiple outputs, power and voltage ratings, size, protections, etc. A prototype has been fully developed and tested as a PC power supply. The autonomy achieved at full power is around 7 minutes.

New active input current shapers to allow AC-to-DC converters with asymmetrically driven transformers to comply with the IEC-1000-3-2

Four new topologies of active input current shapers (AICSs) for converters with symmetrically driven transformers (such as half-bridge, full-bridge and push-pull) have been proposed. This paper analyzes the extension of the use of these new AICSs topologies to converters with asymmetrically driven transformers. Using some of these topologies, the size of AICS inductors can be reduced and even integrated in a single magnetic core. As in the case of other converters with AICS circuit, the new topologies allow line current harmonics to be reduced and thereby to comply with the IEC 1000-3-2 specifications, whilst maintaining all the features of standard DC-to-DC converters (e.g., fast transient response). Finally, the proposed topologies have been experimentally tested.

Dynamic limits of a power factor preregulator

Power factor correction has been one of the hottest topics during the last years and hence, many new circuits have appeared. In general, it is assumed that preregulators based on multiplier circuits have poor dynamics and then, a second stage is needed to improve the output voltage dynamic behaviour. The other option is the use of single stage topologies which have fast output voltage regulation although the input current waveform is not sinusoidal. This paper presents an analysis of the dynamic behaviour of a conventional power factor preregulator. The objective is to find the limits of the dynamic characteristics of these circuits when the priority is to improve the output voltage regulation and not the total harmonic distortion or the power factor. A large signal model is presented and the theoretical results are validated with a prototype.

Simple droop voltage control system for parallel operation of UPS

Uninterruptible power supply systems are very valuable nowadays for many reasons as they prevent critical systems from shutting down when the mains fails. Safety systems in airports, hospitals, banks etc cannot be turned off at any moment. As the power needs can grow when systems are upgraded, the UPS rated power should also grow. Then, there are two options: buying a more powerful UPS or upgrading the system adding a new small UPS in parallel. This option is very interesting for manufacturers because it is very versatile and large systems can be powered with small UPS. However, AC paralleling is always controversial because phase and voltage amplitude match should be guaranteed. This paper presents a prototype using a very simple system to allow UPS to be paralleled. When the AC output is obtained from a battery, there is usually a step-up converter to boost the input voltage and a dc-ac stage connected in cascade. Therefore, the output voltage amplitude can be controlled changing the dc bus voltage instead of changing the modulation ratio of the inverter PWM signal, making possible to operate the inverter stage without amplitude regulation. As a consequence, parallel connection of the UPSs becomes similar to paralleling dc converters, and well known methods used in dc-dc converters can also be used in this case. Two 3 kW UPSs prototypes using the proposed system have been built and tested to compare theoretical and experimental results.

Elimination of the Transfer-Time Effects in Line-Interactive and Passive Standby UPSs by Means of a Small-Size Inverter

The main drawback of line-interactive and passive standby uninterruptible power supplies (UPS) is the transfer time when changing from normal mode of operation to battery mode of operation. During this time, the critical loads protected by the UPS are under the influence of the grid disturbance which forced the mode change. On the other hand, equipment protected by a double conversion UPS is never affected by any disturbance in the mains. Nevertheless, the efficiency of this topology is lower and its size and cost are considerably higher. Hence, the elimination of the transfer process between modes in line-interactive and passive standby UPSs would make them more competitive than double conversion topology in many situations. In this paper, a method for eliminating the transfer time is proposed. It is based on a half-bridge inverter with a hysteretic controller whose output voltage is only applied to the load during the transfer time. Considering the random nature of grid failures and the short duration of the transfer time, the design and selection of the components is nothing but typical. This also leads to a non-standard hysteretic controller that needs to be fully analyzed. Experimental results are provided for a 750-W line-interactive UPS with a transfer time of 4 ms.