Arun Chandra

A computational architecture to model human emotions

A computational architecture to model human emotions is described and developed. In previous work on brain modeling there has been significant effort to model the brains analytical and learning capabilities. However, modeling feelings has not been pursued vigorously. The modeling of human emotions and emotional states is key to our ability to create next generation human like agents. The proposed computer architecture is based on Markov modeling theory. This rich mathematical theory provides us with the ability to model emotional states and how they change. We apply this theory and show how a computational engine can be built to model human emotions. A simple emulation of the proposed architecture is implemented in software and some initial results are presented which show the power of this architecture to develop future generation emotion engines.

Evaluating HACMP/6000: a clustering solution for high availability distributed systems

The requirements for highly available computer systems have evolved over time. In a commercial environment end-users and consumers do not tolerate systems that are unavailable when needed. This paper describes and evaluates the High Availability Cluster Multi-Processing (HACMP/6000) product. HACMP/6000 is a clustering solution for high availability distributed systems. Our approach in showing the effectiveness of HACMP/6000 is both qualitative and quantitative. We use availability analysis as a means of our quantitative analysis. Availability analysis is undertaken using a state-of-the-art availability analysis tool-System Availability Estimator (SAVE). Results obtained from the analysis are used for comparison with a non-HACMP/6000 system.

Practical considerations in formal equivalence checking of PowerPC microprocessors

Recently, formal verification has become more a part of the VLSI design methodology. Formally verifying a design guarantees 100% coverage and negates the need to do simulation. Theoretically, 100% coverage is very appealing and formal verification looks to be the panacea to solve the coverage problem. However, there are many practical considerations in deploying formal verification in real design environments. These considerations if not evaluated can lead to ineffective and even erroneous formal verification methodologies. In this paper we show how to make formal verification a successful part of a design methodology by paying attention to practical considerations and knowing the limitations of formal verification. We show the errors that can result by making over generalized assumptions and how they can be avoided. We do this in the context of the design of PowerPC microprocessors. We limit ourselves to a formal verification technique commonly used in our design methodology-boolean equivalence checking.

Using field data to evaluate intrusive repair

In this paper we develop a methodology of using field data to evaluate intrusive repair. Intrusive repair is a phenomena where a repair action causes new failures to occur. Our methodology uses causal diagrams to evaluate intrusive repair. We introduce the concept of a threshold time window and define and evaluate measures for intrusive repair and diagnostic effectiveness. We conduct this study for RS/6000 clients and servers. Care is taken to include all classes of systems. The workstations evaluated, therefore, included representatives from the desktop, deskside, and rack families. For each class of machine, data is extracted from field databases. Our methodology provides a way to characterize intrusive repair and diagnostic effectiveness. This will enable us to identify improvements to make with current products and justify improved service features in future designs. In the future, an activity planned is a way to automate the evaluation process by which the field can be monitored for potential intrusive repair and diagnosability problems.