Asha Balijepalli

CMOS-Compatible SOI MESFETs With High Breakdown Voltage

The authors demonstrate that silicon-on-insulator (SOI) MESFETs can be fabricated alongside SOI CMOS with no changes to the foundry process flow. The MESFETs operate in depletion mode with a threshold voltage of -0.6 V for a gate length of 0.6 mum. The breakdown voltage of the MESFETs greatly exceeds that of the CMOS devices and varies in the range of 12-58 V depending upon the channel access length, i.e., the distance from the edge of the gate to the edge of the drain region. For MESFETs with a gate length of 0.6 mum and an access length of 0.6 mum, the peak cutoff frequency exceeds 7 GHz. The maximum available gain increases with drain bias and values of fmax range from 17 GHz at VDD = 2 V to 22 GHz at VDD = 8 V

Compact modeling of carbon nanotube transistor for early stage process-design exploration

Carbon nanotube transistor (CNT) is promising to be the technology of choice for nanoscale integration. In this work, we develop the first compact model of CNT, with the objective to explore the optimal process and design space for robust low-power applications. Based on the concept of the surface potential, the new model accurately predicts the characteristics of a CNT device under various process and design conditions, such as diameter, chirality, gate dielectrics, and bias voltages. With the physical modeling of the contact, this model covers both the Schottky-barrier CNT (SB-CNT) and MOS-type CNT. The proposed model does not require any iteration and thus, significantly enhances the simulation efficiency to support large-scale design research. Using this model, we benchmark the performance of a FO4 inverter with CNT and 22nm CMOS technology. The following key insights are extracted: (1) even with the SB-CNT and realistic layout parasitics, the circuit speed can be more than 10X that of 22nm CMOS; (2) The diameter range of 1-1.5nm exhibits the maximum tolerance to contact materials and process variations; (3) a CNT circuit allows better scaling of the supply voltage (Vdd) for power reduction. For a fixed energy consumption and Vdd, the CNT speed is 4X that of 22nm CMOS. Overall, the new model enables efficient design research with CNT, revealing tremendous opportunities for both high-speed and low-power applications.

Modeling and analysis of non-rectangular gate for post-lithography circuit simulation

In the nano regime it has become increasingly important to consider the impact of non-rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically increases the leakage current and requires geometry dependent transistor models for post-litho circuit simulation, hi this paper, we propose a coherent modeling approach for non-rectangular gates based on equivalent gate length (Le). A gate-voltage dependent model of Le is developed which is scalable with design conditions, continuous across weak and strong inversion regions, accurate for both leakage and saturation current, and compatible with standard circuit analysis tools. We systematically verify this approach with 65 nm TCAD simulations. A generic CAD algorithm is further proposed to predict the value of Le under various non-rectangular geometries. The interaction with the narrow-width effect is efficiently convolved in this method. Depending on the gate geometry, the leakage current can vary more than 15X at 65 nm technology node. Our analytical method well captures this effect. Finally, we extrapolate the impact of NRG effect on future technology generations. The proposed model can be easily extracted from TCAD tools or direct silicon data. It bridges the gap between lithography, simulation, and circuit analysis for measuring transistor performance under increasingly severe NRG effect.

SILICON-BASED INTEGRATED MOSFETS AND MESFETS: A NEW PARADIGM FOR LOW POWER, MIXED SIGNAL, MONOLITHIC SYSTEMS USING COMMERCIALLY AVAILABLE SOI

Metal Semiconductor Field Effect Transistors fabricated using compound semiconductor materials have important applications in high-speed/low-noise communication systems. However, their integration densities are low compared to silicon technologies, and it is difficult to combine them with conventional CMOS for single-chip, mixed-signal circuit applications. In this paper we describe how silicon-on-insulator MESFETs can be fabricated alongside conventional MOSFETs using a commercially available silicon-on-insulator foundry. The process flow for the integrated MOSFETS and MESFETs is presented. Measurements from MESFETs fabricated using a commercial foundry demonstrate good depletion-mode device operation. The measured data confirms a square-law behavior for the saturated drain current, which can be reproduced using readily available MESFET models for Spice circuit simulation. The Spice model is applied to a simple differential-pair amplifier and the modeled results compared to measured data.

Compact Model of Carbon Nanotube Transistor and Interconnect

A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both I-V and C-V characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1-1.5 nm, the circuit can be more than 8× faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials.

A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design

A compact model for the Carbon nanotube transistor (CNFET) is presented in this work. This simple model aids the first-order analysis for digital and analog design with CNFET. Based on the physical understanding of ballistic transport in the CNFET channel and tunneling at the Schottky barrier contacts, we develop a set of closed- form expressions that predict the device behavior with varying process and bias conditions. Using this model, we compare a CNFET with 22 nm MOSFET in both digital and analog domains. We conclude that (1) a CNFET digital circuit can be more than 1 OX faster than 22 nm CMOS; (2) there is 1 OX improvement in gmfor comparable device dimensions, and (3) >25X improvement in gosfor comparable saturation current. This simple, scalable model is an efficient tool for analytical treatment of CNFET based circuits, revealing potential design opportunities, especially in the analog domain.

Total dose radiation response of CMOS compatible SOI MESFETs

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a silicon-on-insulator (SOI) CMOS process. The MESFETs make use of a TiSi/sub 2/ Schottky gate and display good depletion mode characteristics with a threshold voltage of -0.5 V. The drain current can also be controlled by a voltage applied to the substrate, which then behaves as a MOS back gate. The transistors have been irradiated with 50 keV X-rays to a total ionizing dose in excess of 1 Mrad(Si). After irradiation the threshold voltage of both the top Schottky gate and the back MOS gate shift to more negative values. The shift in threshold is attributed to radiation induced fixed oxide charge at the interface between the SOI channel and the buried oxide.

Compact modeling of a PD SOI MESFET for wide temperature designs

A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of -180 to 150^oC. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquints Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications.

High-Voltage CMOS Compatible SOI MESFET Characterization and Spice Model Extraction

A mature and well-established SOI CMOS process has been used to fabricate metal-semiconductor field-effect transistors (MESFETs) that operate in the gigahertz range. These 0.6mum depletion-mode SOI MESFETs exhibit a maximum breakdown voltage of 45V in spite of being fabricated using the standard 3.3V CMOS process. This high voltage capability makes the device a strong contender for applications such as power amplifiers, voltage controlled oscillators and DC-DC converters. DC and RF characterization involving breakdown voltage measurements, S-parameter measurements and small-signal parameter extraction was conducted on the device. We have customized an advanced, commercially available TOM3 SPICE MESFET model to represent the SOI MESFET. Based on extracted small-signal parameters, a simplified method to extract the charge parameters of the TOM3 capacitance model was developed. A diode subcircuit has been proposed to model the breakdown mechanism in the SOI MESFET

The Predictive Technology Model in the Late Silicon Era and Beyond

The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. This new paradigm requires the Predictive Technology Model (PTM) for future technology generations, including nanoscale CMOS and post-silicon devices. This paper presents a comprehensive set of predictive modeling developments. Starting from the PTM of traditional CMOS devices, it extends to CMOS alternatives at the end of the silicon roadmap, such as strained Si, high-k/metal gate, and FinFET devices. The impact of process variation and the aging effect is further captured by modeling the device parameters under the influence. Beyond the silicon roadmap, the PTM outreaches to revolutionary devices, especially carbon-based transistor and interconnect, in order to support explorative design research. Overall, these predictive device models enable early stage design exploration with increasing technology diversity, helping shed light on the opportunities and challenges in the nanoelectronics era.