Åshild Grønstad Solheim

On the Potential of NoC Virtualization for Multicore Chips

As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are a reality. Within the context of these multi-core chips, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metrics is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics in the NoC context as well. In this paper we identify and discuss the main properties that a NoC must exhibit in order to enable such optimizations. In particular, we propose the use of virtualization techniques at the NoC level. AS a major finding, we identify the implementation of routing algorithms to become a key design parameter in order to achieve an effective virtualization of the chip should also supporting broadcast within the virtualized context. The intention behind this paper is for it to serve as a position paper on the topic of virtualization for NoC and the challenges that should be met at the routing layer in order to maximize performance, fault-tolerance and power consumption in multicore chips.

Deadlock-Free Dynamic Network Reconfiguration Based on Close Up*/Down* Graphs

Current high-performance distributed systems use a switch-based interconnection network. After the occurrence of a topological change, a management mechanism must reestablish connectivity between network devices. This mechanism discovers the new topology, calculates a new set of routing paths, and updates the routing tables within the network. The main challenge related to network reconfiguration (the change-over from one routing function to another) is avoiding deadlocks. Former reconfiguration techniques significantly reduce network service. In addition, most recent proposals either need extra network resources (such as virtual channels) or their computation complexities are prohibitive. For up*/down* routed networks we propose a new reconfiguration method that supports a virtually unaffected network service at a minor computational cost. This method is suitable for both source and distributed routing networks, and does neither restrict the injection of packets nor the updating of routing tables during the topology-change assimilation.

Routing-contained virtualization based on Up*/Down* forwarding

Virtualization of computing resources is becoming increasingly important both for high-end servers and multi-core CPUs. In a virtualized system, the set of resources that constitute a virtual compute entity should be spatially separated from each other. Dividing the cores on a chip, or the CPUs in a high end server into disjoint sets for each task is a trivial problem. Ensuring that they use disjoint parts of the interconnection network is, however, complex, and in existing methods the requirement of routing-containment of each virtual partition severely degrades the utilization of the system. In this paper, we present an allocation strategy that is based on Up*/Down* routing. Through simulations, we demonstrate increases (in some cases above 30%) in system utilization relative to state-of-the-art in a Dimension Order routed mesh - a topology that is assumed to be widely deployed in Networks on Chip.

Routing for the asi fabric manager

Advanced Switching Interconnect (ASI) is a protocol-independent switching technology for communication, storage, and embedded computing. The ASI Fabric Manager is responsible for detecting the topology of the ASI network, and computing the routing information and distributing it to the endpoints. In this article we explain the most important requirements for the routing algorithm of the ASI Fabric Manager and illustrate an approach that takes into account recent developments in routing algorithms for interconnect technologies. This approach is evaluated through simulation experiments using the J-Sim environment.

Interconnection Networks: Architectural Challenges for Utility Computing Data Centers

Advancing research will enable an interconnection network to support the same seamless virtualization found in other parts of hardware, such as CPUs. Such a network thus poses particular challenges as well as opportunities for a utility computing data center.

Efficient and Contention-Free Virtualisation of Fat-Trees

Maintaining high system utilisation is a key factor for data centres. However, strictly partitioning the datacentre resources to fully isolate the concurrent applications (contention freedom) leads to poor system utilisation because of fragmentation. We present an allocation algorithm for fat-trees (which are commonly found in large-scale data centres) capable of increasing system utilisation while maintaining application isolation. Results show at least a 10% increase in system utilization compared to regular contention free allocation mechanisms, at the cost of a slight reduction in network performance or application isolation.

Efficient and deadlock-free reconfiguration for source routed networks

Overlapping Reconfiguration is currently the most efficient method to reconfigure an interconnection network, but is only valid for systems that apply distributed routing. This paper proposes a solution which enables utilization of Overlapping Reconfiguration in a source routed environment. We demonstrate how a synchronized injection of tokens has a significant impact on the performance of the method. Furthermore, we propose and evaluate an optimization of the original algorithm that reduces (and in some cases even eliminates) performance issues caused by the token forwarding regime, such as increased latency and decreased throughput.

RecTOR: A New and Efficient Method for Dynamic Network Reconfiguration

Reconfiguration of an interconnection network is fundamental for the provisioning of a reliable service. Current reconfiguration methods either include deadlock-avoidance mechanisms that impose performance penalties during the reconfiguration, or are tied to the Up*/Down* routing algorithm which achieves relatively low performance. In addition, some of the methods require complex network switches, and some are limited to distributed routing systems. This paper presents a new dynamic reconfiguration method, RecTOR, which ensures deadlock-freedom during the reconfiguration without causing performance degradation such as increased latency or decreased throughput. Moreover, it is based on a simple concept, is easy to implement, is applicable for both source and distributed routing systems, and assumes Transition-Oriented Routing which achieves excellent performance. Our simulation results confirm that RecTOR supports a better network service to the applications than Overlapping Reconfiguration does.

An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures

The manufacturing process of modern day processors is both costly and complex and there are many different factors that influence the quality of a chip when it comes off the production line. Typically, hundreds of chips are manufactured from a single silicon wafer and as we go deeper into the sub-micron era of microchip manufacturing, the potential for defects during production increases. The advent of multi-core computing may introduce problems related to connectivity and yield for high volume manufacturing (HVM). In this paper we explore potential benefits that fault tolerant routing provides within the NoC (network-on-chip) paradigm with a study of the relationship between connectivity and yield at the interconnect routing level. For dimension-order routing based mesh NoCs, we describe two methods that are logically straightforward to implement and that can be used to increase the yield of chips with interconnect router faults.

A framework for routing and resource allocation in network virtualization

Computer architectures for high performance computing have traditionally been based on an assumption of one parallel application running alone on one machine. The current trend is, however, that huge computer installations offer compute power to a set of users or customers, each demanding only a subset of the available compute resources. This places new requirements on the architecture, in that it must support dynamic partitioning of the resources into several virtual servers as demand changes. We introduce a novel framework which supports flexible formation of such virtual servers while preventing interference between the communication of different virtual servers. This paper investigates the impacts of a shared interconnection network on applications running on virtual compute servers. We show that the interconnect performance supplied to each job is highly unpredictable, and that a job can experience a performance degradation of 97% when its traffic interferes with the traffic of concurrent jobs. With a minor reduction in the utilization of each processing node, this can be considerably improved through a combination of routingcontainment in the interconnection network and a carefully designed resource allocation strategy.