Ashish Sirasao

Exploration and Tradeoffs of different Kernels in FPGA Deep Learning Applications

In the field of deep learning, efficient computational hardware has come to the forefront of the large scale implementation and deployment of many applications. In the process of designing hardware, various characteristics of hardware platforms have been studied in order to best implement the high computational demand, high memory bandwidth, and flexibility of networks. In addition to design space exploration of kernels, kernel design must be seen in the context of full system architectures or in terms of the combination of deep learning and other types of applications whether video encoding/decoding or analytics, speech recognition, or the multitude of potential applications combining deep learning kernels with tightly integrated coprocessor architectures. Kernel sizes, on-chip and off-chip memories, numeric datatypes and efficient compute architectures all must be merged into optimal design choices for both performing computations with maximum efficiency as well as programmable flexibility.

Precision medicine and FPGA technology: Challenges and opportunities

As genomic medicine becomes part of standard clinical care, Precision Medicine faces a daunting computational challenge in scaling up to support the genomic, image processing and analytics workloads required for millions of patients, especially in oncology clinics. Computational solutions based on heterogeneous hardware platforms like FPGAs have the potential to enable rollout of personalized care for large numbers of patients. We review several clinical use cases to shed light on how FPGA-based solutions can lead to large performance gains and tackle the computational bottlenecks in precision medicine. The biggest barrier to FPGA adoption is their accessibility and the steep learning curve for many bioinformatics and precision medicine codebase development groups. We describe new standard libraries and development environments that will facilitate FPGA-based development and show how they enable performance improvements with modest effort investment.