Ashok K. Goel

Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature

Single-electron transistors (SETs) provide current conduction characteristics comparable to CMOS technology and research shows that these devices can be used to develop logic circuits. It has been observed while building logic circuits that comprise only of SETs the voltage at the gate input had to be much higher than the power supply for the SET to have acceptable switching characteristics. This limitation in the gate and power supply voltages makes it practically inappropriate to build circuits. In this paper, we propose a hybrid architecture to overcome this limitation by combining conventional MOS devices with SETs. Three different types of hybrid circuits have been proposed and their characteristics have been studied using SPICE-based simulation tool which includes a SET-SPICE model.

Quantum capacitance extraction for carbon nanotube interconnects

Electrical transport in metallic carbon nanotubes, especially the ones with diameters of the order of a few nanometers can be best described using the Tomanaga Luttinger liquid (TL) model. Recently, the TL model has been used to create a convenient transmission line like phenomenological model for carbon nanotubes. In this paper, we have characterized metallic nanotubes based on that model, quantifying the quantum capacitances of individual metallic single walled carbon nanotubes and crystalline bundles of single walled tubes of different diameters. Our calculations show that the quantum capacitances for both individual tubes and the bundles show a weak dependence on the diameters of their constituent tubes. The nanotube bundles exhibit a significantly large quantum capacitance due to enhancement of density of states at the Fermi level.

Electromigration in the VLSI interconnect metallizations

Electromigration is one of the major failure mechanisms in VLSI interconnect metallizations. It degrades the circuit performance of an integrated circuit by causing open-circuit and short-circuit failures in the interconnections. Several factors that affect electromigration under pulsed DC and AC conditions, such as current density, activation energy, temperature, interconnection material properties, etc. are reviewed. Methods for testing and detecting electromigration are presented, and methods to reduce the effects of electromigration are discussed.<<ETX>>

Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices

Single electron transistor is a nanoelectronic three terminal device. It provides current conduction characteristics comparable to a MOSFET. In this paper, the authors have designed and simulated logic circuit architectures with a combination of SET and conventional devices such as MOSFETs and comparators. The performances of these hybrid architectures and their advantages and disadvantages with SET standalone circuits have also been studied

A new time-position algorithm for the modeling of multilevel carry skip adders in VHDL

It must be noted that, though the concept of carry skip has been around for nearly two decades, interest has been shown only recently to optimize and speed-up the design. This is perhaps indicative of the uniform and efficient VLSI design of the adder. Various approaches, both technology dependent and independent, have been dealt with to optimize the design. Our work improves upon some of the algorithms and results in higher bits per group than reported earlier. These results have been further validated by making models of the adder and simulating them in VHDL. The advantages of using VHDL is the quick time-substitution capability the language has to offer.

Study of quaternary logic versus binary logic

The authors deal with the comparison of quaternary and binary logic with reference to entropy, speed of data transmission and data string length QUATLOG, computer simulator developed, demonstrates the relative advantages of employing quaternary logic for data transmission.<<ETX>>

Design and simulation of logic gates using single electron transistors at room temperature

The Single Electron Transistor (SET) is a nanoscale three terminal device that provides current conduction characteristics comparable to a MOSFET and can be used for developing nanoscale logic circuits. In this paper, we have determined the design parameters of an SET to observe current oscillations at room temperature. These parameters have been used to design SET-based logic gates for room temperature operation. The circuit architectures of the proposed SET-based logic gates are identical to the corresponding CMOS gates. Complementary operations of an SET as n- and p-type devices were achieved by controlling the charge on the SET island by using the appropriate tuning gate voltages. We have proposed room temperature designs for the NOT, NOR, NAND, And-Or-Invert (AOI) and Or-And-Invert (OAI) gates. Their operations have been verified by simulations with a SPICE package which includes the SET-SPICE model.

Comparison of NMOS, CMOS and GaAs technologies

The relative merits of silicon NMOS, CMOS, and GaAs technologies are discussed. The relative commercial standings of these IC technologies are discussed.<<ETX>>

Electrostatic capacitance extraction for carbon nanotube interconnects

Carbon nanotubes are promising candidates for futuristic nanoelectronic applications due to their excellent properties. In this paper, we present a comprehensive modeling and calculation of electrostatic capacitances for various carbon nanotube systems that can be used to model interconnects in nanotechnology circuits. We provide results for single walled, multiwalled and bundles of single-walled carbon nanotubes as functions of the various design parameters. Numerical computations were performed using the method of moments in conjunction with a Greenpsilas function appropriate for the geometry of the interconnects.

Modeling of crosstalk and propagation delays in the crossing interconnections on GaAs-based VHSICs

We have developed computer-efficient models of the crosstalk effects and propagation delays associated with the bilevel crossing interconnections on GaAs-based VHSICs. The interconnections on the first and second levels were modeled by a combination of lumped circuit parameters and distributed circuit transmission lines. The ground and coupling capacitances used in the model include the fringing fields as well the effects of shielding by the neighboring interconnections. These were determined by the method of moments in conjunction with a Greens function appropriate for the geometry of the interconnections.<<ETX>>