Ashraf W. Lotfi

A 20MHz monolithic DC-DC converter manufactured with the first commercially viable silicon magnetics technology

This paper presents a Power System on Chip (Power-SoC), switch-mode DC-DC synchronous buck converter with switching frequency of 20 MHz, which monolithically integrates high-speed power MOSFET switches, controller and drive circuits, the compensation network, and more importantly, a silicon-based inductor. The new device implements a type III voltage mode control scheme with wide loop bandwidth, which offers ultra-fast transient with tiny small ceramic capacitor and ultra-low ripple (> 8mV peak-peak). The compact design facilitates encapsulation in a 3×4.5×0.9 mm DFN package, while its high efficiency eliminates the necessity of a heat sink. The fully integrated design only requires input and output capacitors, and offers an excellent size and cost-effective alternative to a comparable LDO for high-speed transient and noise sensitive applications. The controller chip is fabricated in a standard 0.25µm CMOS process including high speed, high voltage LDMOS devices used for the integrated power switches. The proprietary magnetics-on-silicon inductor is implemented using a magnetic alloy on silicon die mounted on a substrate coil-in-package to achieve an ultrasmall solution. Performance results show that the new converter can provide up to 1000mA of continuous DC output current, at up to 90% peak efficiency in Pulse-Width-Modulation (PWM) mode. The device is in production with the first commercially viable silicon magnetics technology deployed in a standard foundry.

High frequency loss evaluation in high frequency multi-winding power transformers

A high frequency power transformer (HFPT) with twin secondaries is generally analyzed with each primary ampere-turn being canceled by an equal contribution from each of the two secondaries. Such a methodology does not indicate worst case high frequency losses. This paper analyzes a high frequency power transformer (HFPT) with twin secondaries under a number of interleaving sequences. Each sequence is analyzed under five loading conditions. Under different conditions the primary ampere-turns are canceled by unequal contribution from each of the two secondaries. It is shown that the worst case high frequency losses occur when there is an extreme case of unbalance between the two secondaries.<<ETX>>

A universal self-calibrating Dynamic Voltage and Frequency Scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs

Field Programmable Gate Arrays (FPGAs) are widely used in telecom, medical, military and cloud computing applications. Unlike in microprocessors, the routing and critical path delay of FPGAs is user dependent. The design tool suggests a maximum operating frequency based on the worst-case timing analysis of the critical paths at a fixed nominal voltage, which usually means there is significant voltage or frequency margin in a typical chip. This paper presents a universal offline self-calibration scheme, which automatically finds the FPGA frequency and core voltage operating limit at different self-imposed temperatures by monitoring design-specific critical paths. These operating points are stored in a calibration table and used to dynamically adjust the frequency and core voltage according to the FPGA temperature when the application circuit is running. The self-calibration process is demonstrated on an Altera Cyclone IV 65-nm FPGA with a digitally controlled dc-dc converter, leading to 40% power savings in a typical digital filter application.