Asif Islam Khan

Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures

We report a proof-of-concept demonstration of negative capacitance effect in a nanoscale ferroelectric-dielectric heterostructure. In a bilayer of ferroelectric Pb(Zr0.2Ti0.8)O3 and dielectric SrTiO3, the composite capacitance was observed to be larger than the constituent SrTiO3 capacitance, indicating an effective negative capacitance of the constituent Pb(Zr0.2Ti0.8)O3 layer. Temperature is shown to be an effective tuning parameter for the ferroelectric negative capacitance and the degree of capacitance enhancement in the heterostructure. Landau’s mean field theory based calculations show qualitative agreement with observed effects. This work underpins the possibility that by replacing gate oxides by ferroelectrics in nanoscale transistors, the sub threshold slope can be lowered below the classical limit (60 mV/decade).

Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation

A design methodology of ferroelectric (FE) negative capacitance FETs (NCFETs) based on the concept of capacitance matching is presented. A new mode of NCFET operation, called the “antiferroelectric mode” is proposed, which, besides achieving sub-60mV/dec subthreshold swing, can significantly boost the on-current in exchange for a nominal hysteresis. Design considerations for different device parameters (FE thickness, EOT, source/drain overlap & gate length) are explored. It is suggested that relative improvement in device performance due to FE negative capacitance becomes more significant in very short channel length devices because of the increased drain-to-channel coupling.

Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length Lg = 100 nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We show that a self-consistent simulation scheme based on Berkeley SPICE Insulated-Gate-FET Model:Common Multi Gate model and Landau-Devonshire formalism could quantitatively match the experimental NC-FinFET transfer characteristics. This also allows a general procedure to extract the effective S-shaped ferroelectric charge-voltage characteristics that provides important insights into the device operation.

Room-temperature negative capacitance in a ferroelectric-dielectric superlattice heterostructure.

We demonstrate room-temperature negative capacitance in a ferroelectric-dielectric superlattice heterostructure. In epitaxially grown superlattice of ferroelectric BSTO (Ba0.8Sr0.2TiO3) and dielectric LAO (LaAlO3), capacitance was found to be larger compared to the constituent LAO (dielectric) capacitance. This enhancement of capacitance in a series combination of two capacitors indicates that the ferroelectric was stabilized in a state of negative capacitance. Negative capacitance was observed for superlattices grown on three different substrates (SrTiO3 (001), DyScO3 (110), and GdScO3 (110)) covering a large range of substrate strain. This demonstrates the robustness of the effect as well as potential for controlling the negative capacitance effect using epitaxial strain. Room-temperature demonstration of negative capacitance is an important step toward lowering the subthreshold swing in a transistor below the intrinsic thermodynamic limit of 60 mV/decade and thereby improving energy efficiency.

Dense Electron System from Gate-Controlled Surface Metal–Insulator Transition

Two-dimensional electron systems offer enormous opportunities for science discoveries and technological innovations. Here we report a dense electron system on the surface of single-crystal vanadium dioxide nanobeam via electrolyte gating. The overall conductance of the nanobeam increases by nearly 100 times at a gate voltage of 3 V. A series of experiments were carried out which rule out electrochemical reaction, impurity doping, and oxygen vacancy diffusion as the dominant mechanism for the conductance modulation. A surface insulator-to-metal transition is electrostatically triggered, thereby collapsing the bandgap and unleashing an extremely high density of free electrons from the original valence band within a depth self-limited by the energetics of the system. The dense surface electron system can be reversibly tuned by the gating electric field, which provides direct evidence of the electron correlation driving mechanism of the phase transition in VO(2). It also offers a new material platform for implementing Mott transistor and novel sensors and investigating low-dimensional correlated electron behavior.

Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory

A spintronic device, called the “strain assisted spin transfer torque (STT) random access memory (RAM),” is proposed by combining the magnetostriction effect and the spin transfer torque effect which can result in a dramatic improvement in the energy dissipation relative to a conventional STT-RAM. Magnetization switching in the device which is a piezoelectric-ferromagnetic heterostructure via the combined magnetostriction and STT effect is simulated by solving the Landau-Lifshitz-Gilbert equation incorporating the influence of thermal noise. The simulations show that, in such a device, each of these two mechanisms (magnetostriction and spin transfer torque) provides in a 90° rotation of the magnetization leading a deterministic 180° switching with a critical current significantly smaller than that required for spin torque alone. Such a scheme is an attractive option for writing magnetic RAM cells.

Low power negative capacitance FETs for future quantum-well body technology

A non-hysteretic NCFET structure using thin quantum well body combines two future trends synergistically. Ultra-thin body is needed to suppress short-channel effects and sub-60mV/decade operation is needed to reduce power consumption drastically. NCFET happens to need ultra-thin body as thin as 0.5nm to achieve 0.3V operation. We used simulation results of thin Si body NCFET to illustrate the possibility of achieving 10pA/μm IOFF, 200uA/um Ion with 0.3V supply voltage. Layered semiconductors would be ideal for this future technology.

Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics

We study the effects of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs (NCFETs). Based on this, we propose the concept of conservative design of NCFETs, where any unintentional yet reasonable and simultaneous variation (~±3%) in ferroelectric parameters does not result in the emergence of hysteresis and causes only a reasonable variation in the ON-current (≤5%) and, within these constraints, the enhancement of ON-current due to the addition of the ferroelectric gate oxide, which is is maximized.

Quantum realization of some quaternary circuits

We present the design of quaternary quantum version of reversible circuits such as Toffoli gate, modified Fredkin gate, mux, demux, encoder-decoder using linear ion realizable quaternary Muthukrishnan-Stroud gates. Our realization of quaternary Toffoli gate is more efficient than the previous realization and other quaternary circuits are realized for the time in literature.

Nonvolatile memory design based on ferroelectric FETs

Ferroelectric FETs (FEFETs) offer intriguing possibilities for the design of low power nonvolatile memories by virtue of their three-terminal structure coupled with the ability of the ferroelectric (FE) material to retain its polarization in the absence of an electric field. Utilizing the distinct features of FEFETs, we propose a 2-transistor (2T) FEFET-based nonvolatile memory with separate read and write paths. With proper co-design at the device, cell and array levels, the proposed design achieves non-destructive read and lower write power at iso-write speed compared to standard FE-RAM. In addition, the FEFET-based memory exhibits high distinguishability with six orders of magnitude difference in the read currents corresponding to the two states. Comparative analysis based on experimentally calibrated models shows significant improvement of access energy-delay. For example, at a fixed write time of 550ps, the write voltage and energy are 58.5% and 67.7% lower than FERAM, respectively. These benefits are achieved with 2.4 times the area overhead. Further exploration of the proposed FEFET memory in energy harvesting nonvolatile processors shows an average improvement of 27% in forward progress over FERAM.