Aspi B. Wadia

Reliability Modeling for Fault-Tolerant Computers

Reliability modeling and the mathematical equations involved are discussed for general computer systems organized to be fault tolerant. This paper summarizes the work done over the last four years on mathematical reliability modeling by the authors.

Logic Design for Dynamic and Interactive Recovery

Recovery in a fault-tolerant computer means the continuation of system operation with data integrity after an error occurs. This paper delineates two parallel concepts embodied in the hardware and software functions required for recovery; detection, diagnosis, and reconfiguration for hardware, data integrity, checkpointing, and restart for the software. The hardware relies on the recovery variable set, checking circuits, and diagnostics, and the software relies on the recovery information set, audit, and reconstruct routines, to characterize the system state and assist in recovery when required. Of particular utility is a handware unit, the recovery control unit, which serves as an interface between error detection and software recovery programs in the supervisor and provides dynamic interactive recovery.

Modeling of a Bubble-Memory Organization with Self-Checking Translators to Achieve High Reliability

This paper reports a study on the design and modeling of a highly reliable bubble-memory system. This system has the capability of correcting a single 16-adjacent bit-group error resulting from failures in a single basic storage module (BSM), and detecting with a probability greater than 0.99 any double errors resulting from failures in BSMs. The encoding/decoding network (memory translator) is designed to be self-checking, i.e., a single circuit failure in the translator wiH not produce an erroneous output that goes undetected. The system is able to perform reliable configuration in the event of uncorrectable BSM failures, memory translator failures, and dual-memory buffer failures; even in the presence of a single failure in the status registers controlling the configuration network. The bubble memory under study permits serial accessing of the store with 64 x 1024 bit blocks at a 100-kHz rate. The objective of this study is to develop good fault-tolerant design and analysis methods adequate for newly emerging technologies and prove the practicality by example. The reliability modeling study justifies the design philosophy adopted of employing memory data encoding and a translator to correct single group errors and detect double group errors to enhance the overall system reliability. By a proper design of the memory translator based on a new checking technique, a uniformly high percentage of multiple b-adjacent bit-group error detection is achieved through the use of a proposed code (detects 99.99695 percent of double b-adjacent bit-group errors and 99.9985 percent of triple or more b-adjacent bit-group errors).

Error correction scheme for telephone line transmission of RELP vocoder

This paper presents a scheme for encoding the output bits of an 8500 bps residual excited linear predictive coder (RELPC), in which the quality of the synthesized speech is more sensitive to errors in certain bits. Fifty-two of the 272 bits in a 32 ms voice frame were identified as most critical and in need of protection. A Burst-trapping code, using a (21,14) Single Error Correcting Double Error Detecting shortened Cyclic Hamming code as the basic block code was constructed. The code was selected with due consideration to computational load, delay in decoding and total bit rate requirement of less than 9.6 kbs. The paper also describes a Markov model for the decoding process and then determines the improvement in quality resulting from the use of the above scheme. In particular a bit error rate of 5 × 103is reduced to 3 × 106and a burst error rate of 5 × 104is reduced to 6.8 × 105. Some of the effects of errors on auditory perception which appear counter intuitive are briefly discussed.

Generation of node lists using segment analysis

This paper presents two straightforward algorithms for generating node lists for reducible graphs. The algorithms are much simpler than those of Aho and Ullman [1]. The length of the node list produced by the algorithms given here is bounded above by (d + 1)n, where n is the number of nodes in the graph and d is the number of nodes that are tails of back edges. For realistic programs, however, the algorithms given here produce much shorter node lists, generally of length less than 3n. This paper emphasizes simplicity of the algorithms.