Astrit Ademaj

The time-triggered Ethernet (TTE) design

This paper presents the rational for and an outline of the design of a time-triggered (TT) Ethernet that unifies real-time and non-real-time traffic into a single coherent communication architecture. TT Ethernet is intended to support all types of applications, from simple data acquisition systems, to multimedia systems up to the most demanding safety-critical real-time control systems which require a fault-tolerant communication service that must be certified. TT Ethernet distinguishes between two traffic categories: the standard event-triggered Ethernet traffic and the time-triggered traffic that is temporally guaranteed. The event triggered traffic in TT Ethernet is handled in conformance with the existing Ethernet standards of the IEEE. The design of TT Ethernet has been driven by the requirement of certification of safety-critical configurations and an uncompromising stand with respect to the integration of legacy applications and legacy Ethernet hardware.

Evaluation of fault handling of the time-triggered architecture with bus and star topology

Arbitrary faults of a single node In a time-triggered architecture (TTA) bus topology system may cause error propagation to correct nodes and may lead to inconsistent system states. This has been observed in validation work using software implemented fault injection (SWIFI) and heavy-ion fault injection techniques in a TTA cluster. In a TTA system, the membership and the clique avoidance algorithms detect state inconsistencies and force the nodes that do not have the same state with the state of majority of nodes, to restart. Changing the interconnection structure of the cluster to a star topology allows the use of star couplers that will isolate faults of a node, thus guaranteeing consistency, even in the presence of arbitrary node failures. The same SWIFI and heavy-ion fault injection experiments that caused error propagation in bus-based TTA clusters, were performed in the star configuration. No error propagation was observed in a TTA system with the star topology during the execution of SWIFI and heavy-ion experiments.

A Time-Triggered Ethernet (TTE) Switch

This paper presents the design of a time-triggered Ethernet (TTE) switch, which is one of the core units of the time-triggered Ethernet system. Time-triggered Ethernet is a communication architecture intended to support event-triggered and time-triggered traffic in a single communication system. The TTE switch distinguishes between two classes of traffic. The event-triggered (ET) traffic is handled in conformance with the existing Ethernet standard, while the time-triggered (TT) traffic is transmitted with temporal guarantees. A TTE switch is used in the time-triggered Ethernet system for exchanging time-triggered messages in a time-predictable way while continuing the support of standard Ethernet traffic in order to use existing networking protocols such as IP, UDP or IPX without any modifications. In this paper we present the mechanisms the TTE switch uses to guarantee a constant transmission delay for time-triggered traffic. Also an experimental validation of these mechanisms is given

Slightly-off-specification failures in the time-triggered architecture

Slightly-off-specification (SOS) failures can occur at the interface between the analog and the digital world. If an erroneous node in a distributed system produces an output signal (in time or value) slightly outside the specified window, some nodes will correctly receive this signal, while others might fail to receive it. Such a scenario will result in an inconsistent state of the distributed system. We present the observed temporal SOS failures in the time-triggered architecture with the bus interconnection structure during the execution of the software implemented fault injection in the TTP/C communication controller. Solutions to avoid the occurrence of the temporal SOS failures in the time-triggered architecture are analyzed and presented.

A Tunable Add-On Diagnostic Protocol for Time-Triggered Systems

We present a tunable diagnostic protocol for generic time-triggered (TT) systems to detect crash and send/receive omission faults. Compared to existing diagnostic and membership protocols for TT systems, it does not rely on the single-fault assumption and tolerates malicious faults. It runs at the application level and can be added on top of any TT system (possibly as a middleware component) without requiring modifications at the system level. The information on detected faults is accumulated using a penalty/reward algorithm to handle transient faults. After a fault is detected, the likelihood of node isolation can be adapted to different system configurations, including those where functions with different criticality levels are integrated. Using actual automotive and aerospace parameters, we experimentally demonstrate the transient fault handling capabilities of the protocol.

Segmentation of standard ethernet messages in the time-triggered ethernet

TT Ethernet is a communication architecture which allows the integration of the standard Ethernet traffic and real-time Ethernet traffic in the same network without invalidating the real-time properties of the real-time traffic. The TT Ethernet switch distinguishes between two classes of traffic. The standard Ethernet traffic is handled in conformance with the existing (standard) Ethernet, whereas the real-time traffic is transmitted with a constant transmission delay. In order to guarantee a constant message transmission delay, the TT Ethernet switch preempts, if necessary, the transmission of standard Ethernet messages, and retransmit the preempted Ethernet message as soon as the transmission of the real-time Ethernet message is finished. The message can be preempted several times before it is successfully transmitted, which decreases the throughput of standard Ethernet messages. In this paper, we propose a segmentation mechanism for standard Ethernet frames in order to increase the throughput. The segmentation mechanism does not change the format of Ethernet frame and is transparent to higher levels of a protocol stack such as TCP/IP.

Hardware Implementation of the Time-Triggered Ethernet Controller

Time-triggered (TT) Ethernet is a novel communication system that integrates real-time and non-real-time traffic into a single communication architecture. A TT Ethernet system consists od a set of nodes interconnected by a specific switch called TT Ethernet switch. A node consist of a TT Ethernet communication controller that executes the TT Ethernet protocol and a host computer that executes the user application. The protocol distinguishes between event-triggered (ET) and time-triggered (TT) Ethernet traffic. Time-triggered traffic is scheduled and transmitted with a predictable transmission delay, whereas event-triggered traffic is transmitted on a best-effort basis. The event-triggered traffic in TT Ethernet is handled in conformance with the existing Ethernet standards of the IEEE. This paper presents the design of the TT Ethernet communication controller optimized to be implemented in hardware. The paper describes a prototypical implementation using a custom built hardware platform and presents the results of evaluation experiments.

Fault tolerance evaluation using two software based fault injection methods

A silicon independent C-Based model of the TTP/C protocol was implemented within the EU-founded project FIT. The C-based model is integrated in the C-Sim simulation environment. The main objective of this work is to verify whether the simulation model of the TTP/C protocol behaves in the presence of faults in the same way as the existing hardware prototype implementation. Thus, the experimental results of the software implemented fault injection applied in the simulation model and in the hardware implementation of the TTP/C network have been compared. Fault injection experiments in both the hardware and the simulation model are performed using the same configuration setup, and the same fault injection input parameters (fault injection location, fault type and the fault injection time). The end result comparison has shown a complete conformance of 96.30%, while the cause of the different results was due to hardware specific implementation of the built-in-self-test error detection mechanisms.

A maintenance-oriented fault model for the DECOS integrated diagnostic architecture

The increasing use of electronics in the automotive and avionic domain has lead to dramatic improvements with respect to functionality, safety, and cost. However, with this growth of electronics the likelihood of failures due to faults originating from electronic equipment also increases. In order to tackle prevalent diagnostic problems such as the reduction of the fault-not-found ratio, a maintenance-oriented fault model is needed that serves as the basis for the classification of experienced failures. In this paper we introduce such a maintenance-oriented fault model that establishes the conceptual foundation of the diagnostic services of the DECOS integrated architecture. The fault model takes the component-based nature of todays distributed embedded systems into account. According to this model each experienced failure is classified according to the field replaceable units of the system.

Time-Triggered Ethernet and IEEE 1588 Clock Synchronization

The time-triggered Ethernet unifies real-time and non-real-time traffic into a single communication architecture. We have built a prototype implementation of an FPGA TT-Ethernet switch and an FPGA TT Ethernet communication controller supporting a network bandwidth of 100 Mbit/sec. Time-Triggered Ethernet introduces two message classes, i) the standard event-triggered Ethernet messages, denoted as ET messages, and ii) the time-triggered Ethernet messages, denoted as TT messages. All TT messages are transmitted periodically and are scheduled a priori in a way that there are no conflicts on the network. The network handles these messages according to the cut-through paradigm. Computer nodes containing TT Ethernet communication controllers establish and maintain global time base. However nodes containing standard Ethernet controllers can be connected to a TT Ethernet system and can send ET messages without affecting the temporal properties of the TT messages. The global time format of the TT Ethernet deploys the UTC time format which is compatible with the time format of the IEEE 1588 standard. In these work we present how we deploy the IEEE 1588 in order to synchronize the TT Ethernet controllers which require a tight synchronization among them. Additionally the IEEE 1588 clock synchronization based protocol will be implemented at standard Ethernet controllers such that they can be establish and maintain a global time base.