Atsushi Hatabu

Parallelization of H.264 video decoder for embedded multicore processor

This paper presents two parallelization methods for H.264 video decoder software on an embedded multicore processor. In parallelizing the H.264 video decoder software on a typical embedded multicore processor with shared memory, there are two problems. One problem is the computational load imbalance among cores. The other problem is memory access contention. The first method is coarse, flexible partitioning adapted for the H.264 decoding functions, which can balance the load with only a small number of synchronizations. The second method is preloading based on predicting the execution time, which can reduce memory access contention and the redundant waiting time for other cores. Experimental results demonstrate that our proposed two methods can achieve significant improvement of the consumed cycles for decoding H.264 bitstreams of QVGA size from 217 to 96 Mcps (2.3 times speedup) as compared to a non-parallel decoder.

QVGA/CIF resolution MPEG-4 video codec based on a low-power and general-purpose DSP

This paper describes a quarter video graphic array/common intermediate format (QVGA/CIF) resolution MPEG-4 video codec based on a low-power, general-purpose digital signal processor (DSP) (NEC μPD77210, 160 MHz, 80 mW, 1.5 V). To enhance video codec performance, the codec employs fast algorithms, including, in motion estimation, a successive similarity detection algorithm (SSDA; a fast block matching) whose decision timing for termination of block matching is optimized. Further, the use of a software direct memory access (DMA) queue reduces the wasteful DSP wait cycles that can result from massive access to external frame memories. The resulting codec executes QVGA (320 × 240 pixels) × 15 fps codec, or CIF (352 × 288 pixels) × 15 fps encoding at 384 kbps, in real time, performance levels sufficient for next-generation wireless videotelephony.

Statistical mechanical analysis of the Kronecker channel model for multiple-input multiple-output wireless communication.

The Kronecker channel model of wireless communication is analyzed using statistical mechanics methods. In the model, spatial proximities among transmission/reception antennas are taken into account as certain correlation matrices, which generally yield nontrivial dependence among symbols to be estimated. This prevents accurate assessment of the communication performance by naively using a previously developed analytical scheme based on a matrix integration formula. In order to resolve this difficulty, we develop a formalism that can formally handle the correlations in Kronecker models based on the known scheme. Unfortunately, direct application of the developed scheme is, in general, practically difficult. However, the formalism is still useful, indicating that the effect of the correlations generally increase after the fourth order with respect to correlation strength. Therefore, the known analytical scheme offers a good approximation in performance evaluation when the correlation strength is sufficiently small. For a class of specific correlation, we show that the performance analysis can be mapped to the problem of one-dimensional spin systems in random fields, which can be investigated without approximation by the belief propagation algorithm.

Statistical mechanical analysis of the linear vector channel in digital communication

A statistical mechanical framework to analyze linear vector channel models in digital wireless communication is proposed for a large system. The framework is a generalization of that proposed for code-division multiple-access systems in Takeda et al (2006 Europhys. Lett. 76 1193) and enables the analysis of the system in which the elements of the channel transfer matrix are statistically correlated with each other. The significance of the proposed scheme is demonstrated by assessing the performance of an existing model of multi-input multi-output communication systems.

H.264 Video Encoder Implementation on a Low-power DSP with Low and Stable Computational Complexity

This paper describes the implementation of an H.264 video encoder designed for use on a low-power DSP core (NEC Electronics Corporations SPXK6) for mobile equipment, which offers not only low computational complexity but small load fluctuation between average and peak load. In order to reduce the high degree of complexity that H.264 ordinarily requires, the encoder employs fast coding methods, including diamond motion searches, and fast decisions based on current-image smoothness as to which type of coding to employ. Further, to suppress increases in peak loads which would degrade real-time encoding performance, feedback-based control of computational complexity is used in motion estimation and intra/inter coding type decisions. On an SPXK6 DSP, the encoder performs H.264 baseline profile video coding at a QVGA (320times240 pixels) resolution of 15 fps, for an average load of 104 M cycle/sec, excluding memory access cycles, with the suppressed peak load increasing by only 20% over that of the average load

Optimization of decision-timing for early termination of SSDA-based block matching

This paper describes an analysis-based method for optimizing the timing of decisions regarding early termination of block matching (BM) in the application of a successive similarity detection algorithm (SSDA). Although the SSDA reduces BM computational costs, making decisions to terminate BM or not consumes additional processor cycles. Here, total costs, including cycles for decisions, are formulated through use of a decision interval, processor-dependent cost factors, and a function which gives probabilities of BM termination. The optimal decision interval is derived by minimizing the cost function. Experiments on MPEG-4 video coding show the proposed method facilitates comparative evaluation of the computational costs of SSDA-based BM for various processors.