Atul Kumar Srivastava

A Novel Weighted Diffusion Filtering Approach for Speckle Suppression in Ultrasound Images

Ultrasound images mainly suffer from speckle noise which makes it difficult to differentiate between small details and noise. Conventional anisotropic diffusion approaches tend to provide edge sensitive diffusion for speckle suppression. This paper proposes a novel approach for removal of speckle along with due smoothening of irregularities present in the ultrasound images by modifying the diffusion coefficient in anisotropic diffusion approach. The present work proposes a diffusion coefficient which is a function of difference of instantaneous coefficient (of variation) and the coefficient of variation for homogeneous region. The finally reconstructed image is obtained by weighted addition of the response of proposed anisotropic diffusion filter and the Laplacian filtered image. Simulation results show that performance of the proposed approach is significantly improved in comparison to recently developed anisotropic diffusion filters for speckle suppression.

A Modified Speckle Suppression Algorithm for Breast Ultrasound Images Using Directional Filters

Speckle noise in ultrasound images (US) is a serious constraint leading to false therapeutic decision making in computer aided diagnosis. This highlights the utility of speckle suppression along with due preservation of edges as well as textural features while processing breast ultrasound images (for computer aided diagnosis of breast cancer). This paper presents a modified speckle suppression algorithm employing directional average filters for breast ultrasound images in homogeneity domain. The threshold mechanism during the process is adjusted using the entropies of foreground and background regions to ensure appropriate extraction of textural information. Simulation results demonstrate significantly improved performance in comparison to recently proposed methods in terms of speckle removal as well as edge preservation.

Despeckling of ultrasound images using non-linear conductance function

This paper presents a novel anisotropic diffusion (AD) filter for despeckling of ultrasound images using a non-linear conductance function. Proper choice of the conductance function while applying AD filters is extremely critical. This work proposes an improved conductance function that tends to suppress speckle with due preservation of diagnostic features. The diffusion coefficient of the AD filter thus decreases monotonically and acts as an edge seeking as well as preserving function. Peak Signal to Noise Ratio (PSNR), Coefficient of Correlation (CoC) and Speckle Suppression Index (SSI) are the quality metrics used for performance evaluation of the proposed despeckling filter.

A combinatorial digital circuit with evolutionary algorithm for evolvable hardware software codesign

The theory of evolution is equally well applied on the electronic digital circuit configuration. The genetic algorithm (GA) is an optimization and search technique based on the principles of genetics and natural selection. Genetic algorithm one of the classifications of evolutionary algorithm, is an upcoming area for the designing of reprogrammable hardware. The fitness function decides whether to accept new chromosome for the next generation or not. These functions incorporate various factors that evolve a constrained and much optimized hardware. Our aim in this paper is to present a simple method to synthesize a combinatorial digital circuit with some fitness functions required for any VLSI circuit and reduce the gate complexity of the circuit.

Design and simulation of virtual reconfigurable circuit for a Fault Tolerant System

Evolvable Hardware (EHW) refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. This paper presents a new approach to on-line fault tolerance via reconfiguration of the Programmable Elements (PE) mapped onto field programmable gate arrays (FPGAs). A grid of PE is programmed on the FPGA structure. A complete hardware implementation of an evolvable combinational unit for FPGAs is then performed. The proposed combinational PE grid on FPGA is used as virtual reconfigurable circuit (VRC). Cartesian Genetic Programming (CGP), genetic operators are described in Verilog - HDL and used to reprogram the VRC. In all the cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, with a maximum delay of 22.82ns (when logic level is 16) which is 40% lower than previous attempts. The design parameters of the proposed architecture are also discussed. The fault detection, based on self-checking technique can detect the faults of PEs and routing interconnections in the FPGAs concurrently with the normal system work. After locating the faulty PE, the VRC will be reconfigured using reserved PEs.

Generating test patterns for fault detection in combinational circuits using genetic algorithm

In this paper we propose a method for the automatic test pattern generation for detecting stuck-at-faults in combinational VLSI circuits using genetic algorithm (GA). Derivation of minimal test sets helps to reduce the post-production cost of testing combinational circuits. The GA proves to be an effective algorithm in finding optimum number of test patterns from the highly complex problem space. In this paper results are obtained for single stuck-at-fault in the ISCAS 1989(C17) benchmark circuit.

FPGA Implementation of Image Enhancement Techniques

The objective of this paper is designing, modeling, simulation and synthesis of four Image Enhancement techniques on FPGA. Image Enhancement Algorithms can be classified as point processing Techniques, in which operation is done on pixel level and Spatial Filtering Technique, in which operation is performed within neighborhood of a pixel. Algorithms of all the techniques are studied and hardware circuits are realized for them. Then hardware logic is modeled in Matlab Simulink using Xilinx System Generator Block set and synthesized onto Virtex4 xc4vsx35-10ff668 FPGA chip. Using hardware co-simulation feature of FPGA kit, the algorithms developed are validated.

Cluster growth technique for combinatorial evolvable digital circuits

The genetic algorithm (GA) is one of the optimization techniques of evolutionary algorithm used to design evolvable hardware. This paper proposes the application of cluster based growth approach with genetic algorithm for evolvable hardware. Earlier methods of evolving hardware proposed on static m × n grid structure of hardware that is evolved by reconfiguring interconnections. Clustering technique is a synthesis method where the hardware functionality is evaluated for minimum number of gates. The cluster grows by adding more gates into the cluster if the functionality is not obtained. Reconfiguration of interconnections is also preformed along with the cluster growth. Our main contributions are: 1) Adaptation of genetic operators in a way suitable for clustering growth. 2) Applications to task with unknown number of clusters in Clustering with genetic algorithm and demonstrate its performance. 3) To obtain the desired functionality with least number of logic gates such that the interconnection of nodes in the earlier defined architecture is modified with clustering, so that the fast convergence is obtained.