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Featured researches published by Avinash Sodani.
Intel Xeon Phi Processor High Performance Programming (Second Edition)#R##N#Knights Landing Edition | 2016
Jim Jeffers; James Reinders; Avinash Sodani
Explores Lattice QCD (Quantum Chromodynamics), which models the nuclear strong force that binds matter together, on Knights Landing. Optimization and performance results are discussed.
Intel Xeon Phi Processor High Performance Programming (Second Edition)#R##N#Knights Landing Edition | 2016
Jim Jeffers; James Reinders; Avinash Sodani
Weather Research and Forecasting (WRF) Model results on Knights Landing are discussed. Results highlight the performance and development benefits of high bandwidth package memory coupled with processor centric (hostless/non-offload) programming.
Intel Xeon Phi Processor High Performance Programming (Second Edition)#R##N#Knights Landing Edition | 2016
Jim Jeffers; James Reinders; Avinash Sodani
Introduces the Intel Vectorization Advisor, which provides AVX-512 analysis capabilities to help reach the vectorization potential of Knights Landing. For scalar loops, it helps to discover what prevents code from being vectorized. For vectorized loops, it provides detailed AVX-512 performance characterization. Recommendations are additionally supplemented with the AVX-512 Traits and FLOPs, masks, Roofline, and Gather/Scatter reports.
Intel Xeon Phi Processor High Performance Programming (Second Edition)#R##N#Knights Landing Edition | 2016
Jim Jeffers; James Reinders; Avinash Sodani
Visualizations of large data sets are best done on processors, and this chapter explains why and how by highlighting three key open source libraries that are fundamental for SDVis work (i.e., OpenSWR, Embree, and OSPRay). These libraries benefit from the SDVis capabilities of Knights Landing.
Intel Xeon Phi Processor High Performance Programming (Second Edition)#R##N#Knights Landing Edition | 2016
Jim Jeffers; James Reinders; Avinash Sodani
Tuning advice that is specific to the Knights Landing design, which is known as the microarchitecture and is abbreviated as μarch. Focuses on tuning advice arising specifically from the Knights Landing μarch design when compared with the Knights Corner μarch (found in the first-generation Intel Xeon Phi products) or the μarch of a recent Intel® Xeon® processor.
Intel Xeon Phi Processor High Performance Programming (Second Edition)#R##N#Knights Landing Edition | 2016
Jim Jeffers; James Reinders; Avinash Sodani
Takes a look at Partitioned Global Address Space (PGAS) programming models, which scale across cores and nodes while preserving a shared memory-like programming model. While Knights Landing will be programmed mostly with MPI, OpenMP, and TBB, utilizing PGAS models will be increasingly important in the future. Examples illustrate that PGAS can be an effective programming model for the large number of cores on a Knights Landing.
Intel Xeon Phi Processor High Performance Programming (Second Edition)#R##N#Knights Landing Edition | 2016
Jim Jeffers; James Reinders; Avinash Sodani
Results using SeisSol, which simulates wave propagation and dynamic ruptures based on the arbitrary high-order accurate derivative discontinuous Galerkin method, on Knights Landing are discussed. The unique combination of the described individual steps allows the acceleration of seismic simulations. Data reorganization and low-level matrix kernel implementations are key.
Intel Xeon Phi Processor High Performance Programming (Second Edition)#R##N#Knights Landing Edition | 2016
Jim Jeffers; James Reinders; Avinash Sodani
Presents performance optimization methods applicable to N-body simulations on Knights Landing. Discusses the optimization of arithmetic expressions, data structures, thread parallelism, and memory traffic on Knights Landing. Results demonstrate that the N-body simulation, previously optimized for parallelism on Knights Corner, achieves most of the performance improvements available with Knights Landing without any code adaptation—only a recompilation is necessary to take advantage of AVX-512.
Intel Xeon Phi Processor High Performance Programming (Second Edition)#R##N#Knights Landing Edition | 2016
Jim Jeffers; James Reinders; Avinash Sodani
Introduces Knights Landing, a many-core processor that delivers massive thread and data parallelism with high memory bandwidth. Knights Landing is the Second Generation of Intel® Xeon Phi™ products using a many-core architecture which both benefits from, and relies on, parallel programming. Key new innovations such as MCDRAM, cluster modes, and memory modes are explained at a high level.
Intel Xeon Phi Processor High Performance Programming (Second Edition)#R##N#Knights Landing Edition | 2016
Jim Jeffers; James Reinders; Avinash Sodani
Introduces Intel® SIMD Data Layout Templates (SDLT) containers (use in place of std::vector). For C++ code, this can offer an effective method to achieve superior performance by increasing vectorization through “AOS to SOA or AOSOA” conversions. This can enhance performance of Knights Landing or any processor. Includes sample codes, and discussion on how to transition from Array of Structures (AOS) to Structure of Arrays (SOA) or Arrays of Structure of Arrays (ASA) utilizing SDLT while maintaining a high-level object-oriented structure.