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Dive into the research topics where Avireni Srinivasulu is active.

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Featured researches published by Avireni Srinivasulu.


IEEE Transactions on Instrumentation and Measurement | 2009

Current Conveyor-Based Square/Triangular Waveform Generators With Improved Linearity

Dipankar Pal; Avireni Srinivasulu; Basab Bijoy Pal; Andreas Demosthenous; Barda Nand Das

Two second-generation current conveyor (CCII+)-based resistance-capacitance (RC) square/triangular waveform generators, which have been derived from their voltage-mode op-amp-based schemes, with independent control of frequency are presented in this paper. Each configuration consists of two positive second-generation conveyors (CCII(+)-ldquoArdquo and CCII(+)-ldquoBrdquo), three resistors, and one floating capacitor that is responsible for better linearity. The frequency of the waveform generators can independently be adjusted with any passive device. The circuits were built with commercially available current feedback operational amplifiers (AD844) and passive components used externally and tested for waveform generation and tunability. The measured results included in the paper show excellent linear variation of frequency as compared with existing reported configurations over the range from 25 Hz to 260 kHz. The configurations that are suitable for very large scale integration (VLSI) realization find application in capacitive and resistive sensors and in neuro-fuzzy systems.


International Journal of Circuit Theory and Applications | 2011

A novel current conveyor-based Schmitt trigger and its application as a relaxation oscillator

Avireni Srinivasulu

The current paper presents a novel Schmitt trigger using two second-generation current conveyors and four resistors and its application as a relaxation oscillator. The performance of the proposed circuit is examined using Cadence and the model parameters of a 0.6µm CMOS process. The obtained results demonstrate excellent agreement with the theoretical values. The measured results based on commercially available current feedback operational amplifiers (AD 844 AN) are included and the non-idealities are also examined. The topology reports low sensitivities and has features suitable for VLSI implementation. Copyright


international symposium on circuits and systems | 2009

Novel current-mode waveform generator with independent frequency and amplitude control

Dipankar Pal; Avireni Srinivasulu; Manish Goswami

In this paper, a novel square/triangular-waveform generator using second generation current conveyer (CCII+), four resistors and a capacitance with independent control of frequency and amplitude are presented. Frequency (time period) can be tuned independently either by the grounded resistors R or R2, or, by the grounded capacitor C over the range of DC to 300 kHz. The performance of the proposed design is explored using SPICE Level 1 models where it demonstrated good agreement with the theoretical results. Measured results using commercially available CCII+ is also included. The topology is suitable for VLSI realization.


international conference on applied electronics | 2014

Quadrature oscillator using operational transresistance amplifier

Chandra Shaker Pittala; Avireni Srinivasulu

Quadrature oscillator based on the operational transresistance amplifier (OTRA) is presented in this paper. The proposed quadrature oscillator circuit uses two OTRAs as main active building blocks and a few external passive components to generate the oscillations. The circuit provides independent control over the condition of oscillation and frequency of oscillation. A prototype circuit is implemented on a laboratory breadboard using commercially available current feedback operational amplifier ICs (AD844 AN) and passive components are connected externally and tested for waveform generation. Both the SPICE simulation and experimental results are given to verify the theoretical analysis.


The Journal of Engineering | 2013

ULPD and CPTL Pull-Up Stages for Differential Cascode Voltage Switch Logic

Avireni Srinivasulu; Madugula Rajesh

Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area on the chip. Second proposed circuit uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This contributes an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results of these two circuits are compared and presented. These circuits are found to be suitable for VLSI implementation.


international conference on circuit power and computing technologies | 2016

A DCCII based square wave generator with grounded capacitor

V. Vijay; Avireni Srinivasulu

A new square wave generator is proposed using second generation differential current conveyor (DCCII). The proposed circuit has single DCCII and three passive components viz, two resistors and a single capacitor. The grounded capacitor feature has made in implementing a proposed waveform generator. Proposed circuit offers electronic tunability of its duty cycle, operating in wide range frequency from a few Hz to few MHz and also has improved linearity. Comparison of proposed circuit features in contrast to existing oscillator circuits are tabulated with relevant discussion and description mentioning prominent significances. Design and simulation is done in Cadence Virtuoso using gpdk 180 nm libraries. AD844AN commercial op-amps are used for experimental validation of the proposed model.


international conference on applied electronics | 2016

CCII+ based novel waveform generator with grounded resistor/capacitor for tuning

Avireni Srinivasulu; Dipankar Pal

This paper presents a new topology for waveform-generation using two current conveyors, and a grounded capacitor or a resistor for tuning. It uses current-conveyors in place of voltage op-amps to offer better linearity, bandwidth, slew rate and thermal stability. Measured results obtained using commercially available devices AD844AN and passive components show excellent linearity and tunability for both grounded resistor and capacitor topologies over the range of interest. Component sensitivity and temperature-sensitivity from -150°C to +150°C are studied. A comparison with existing candidate-designs shows superiority of the proposed design on all aspects. Grounded-connection of tuning components makes digital control easy.


international conference on signal processing | 2015

Two simple sinusoidal oscillators using single Operational Transresistance Amplifier

Chandra Shaker Pittala; Avireni Srinivasulu

This paper illustrates two sinusoidal oscillators based on single Operational Transresistance Amplifier (OTRA). The proposed circuits require a single OTRA and a few passive components to generate the oscillations. The proposed circuits frequency of oscillation and condition of oscillation are given. The proposed circuits have been examined using Cadence 180 nm CMOS model parameters. These circuits have been constructed using commercially available current feedback amplifier (AD844 AN) and later on passive components were connected externally and tested for waveform generation. The results obtained demonstrate excellent agreement with theoretical values.


international conference on communications | 2015

Low voltage, high speed FinFET based 1-bit BBL-PT full adders

T. Nagateja; T. Venkata Rao; Avireni Srinivasulu

Feature size of CMOS technology continues to scale down; new devices like FinFET are experimented and proposed as an alternative device due to its superior characteristics. In this paper we have presented low voltage, high speed 1-bit full adder cells in Branch Based Logic and Pass Transistor (BBL-PT) logic by using FinFET model parameters. In BBL-PT full adder lies a drawback i.e. voltage step existed in sum output. That could be eliminated in the proposed logics by using the diode connected FinFET (D-FinFET) inverter, N-type FinFET inverter and modified current sink restorer structures. Proposed full adder circuits are compared with conventional adder circuits, and proposed circuits have demonstrated the good delay performance. The performance of proposed and other conventional full adder circuits are examined using Cadence and the model parameters of 180 nm CMOS technology with +1.2 V supply rail voltage and 20 nm FinFET model files with +0.6 V supply rail voltage with frequency 100 MHz.


international conference on communications | 2015

A Schmitt trigger based on DDCCTA without any passive components

Ravipati Linitha; Avireni Srinivasulu; V. Venkata Reddy

Among various active building blocks, the Differential Difference Current Conveying Transconductance Amplifier (DDCCTA) is emerging as a very flexible and versatile building blocks for analog circuit design and has been used for realizing a variety of functions. In this paper, a new current-mode electronically-tunable Schmitt trigger circuit is proposed using Differential Difference Current Conveyor Transconductance amplifier (DDCCTA). The proposed Schmitt trigger consists of single DDCCTA block without any passive components which is advantageous from the point of view of an integrated circuit manufacturing. The performance of the proposed Schmitt trigger circuit is examined using Cadence and the model parameters of a 0.18 μm CMOS process.

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Dipankar Pal

Birla Institute of Technology and Science

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Naveen Kumar

Birla Institute of Technology

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