Avraham Chelly

Silicon on insulator photo-activated modulator

In this paper we present a novel concept for a photo-activated modulator device based on silicon on insulator (SOI-PAM) and in which the information is electronic while the modulation command is optical. Free carriers are generated by external illumination in the vicinity of the information channel. A side-gate potential selects the type of carriers controlling the electric resistance of the channel. The channel is surrounded by oxide trenches to avoid cross-talk current. Another side potential clears the control carriers allowing a high-frequency modulation like in a Metal-Oxide-Semiconductor field effect transistor (MOSFET) device. Since the control command is photonic, faster operation rates are anticipated. The proposed device has dimensions of less than 1 cubic micron.

Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

Ultrathin body (UTB) and nanoscale body (NSB) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern.

Nanoscale Silicon-on-Insulator Photo-Activated Modulator Building Block for Optical Communication

The constantly growing use of real-time computing generates constant urge for much faster processors than those which are currently available in the market. Correspondingly, there is an accelerated development of new optics communication related applications and components. The effort to combine those two trends leads to the generation of new optoelectronic nanodevices. Such hybrid devices may allow high operation speed, reduced cross talk and other noises, low operation power, and obviate the need for the existing electro-optical convertors. In this letter, we present the design, simulation, fabrication, and characterization of an optoelectronic device based on silicon which is capable of speeding up the processing capabilities. This novel device is called silicon-on-insulator photo-activated modulator. The nature of the data flow in this device is electronic, while the modulation control command is optic. Since the external voltage in the final configuration design of the device is constant and no RC (electrical average response time) related delay is generated, faster operation rates are anticipated. This novel device can serve as a building block toward the development of optical data processing while breaking through the way to all optic processors based on silicon chips that are fabricated via typical microelectronics fabrication process.

Usage and Limitation of Standard Mobility Models for TCAD Simulation of Nanoscaled FD-SOI MOSFETs

TCAD tools have been largely improved in the last decades in order to support both process and device complementary simulations which are usually based on continuously developed models following the technology progress. In this paper, we compare between experimental and TCAD simulated results of two kinds of nanoscale devices: ultrathin body (UTB) and nanoscale Body (NSB) SOI-MOSFET devices, sharing the same W/L ratio but having a channel thickness ratio of 10 : 1 (46 nm and 4.6 nm, resp.). The experimental transfer I-V characteristics were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a large gate voltage dependent series resistance (). TCAD tools do not usually consider to be either channel thickness or gate voltage dependent. After observing a clear discrepancy between the mobility values extracted from our measurements and those modeled by the available TCAD models, we propose a new semiempirical approach to model the transfer characteristics.

Modeling of Current-Voltage Characteristics of the PhotoactivatedDevice Based on SOI Technology

An analytical model of the silicon on insulator photoactivated modulator (SOI-PAM) device is presented in order to describe the concept of this novel device in which the information is electronic while the modulation command is optical. The model, relying on the classic Shockley’s analysis, is simple and useful for analyzing and synthesizing the voltage-current relations of the device at low drain voltage. Analytical expressions were derived for the output current as function of the input drain and gate voltages with a parameterization of the physical values such as the doping concentrations, channel and oxide thicknesses, and the optical control energy. A prototype SOI-PAM device having an area of 4 μm × 3 μm with known parameters is used to experimentally validate and support the model. Finally, the model allows the understanding of the physical mechanisms inside the device for both dark and under illumination conditions, and it will be used to optimize and to find the performance limits of the device.

Modeling and simulations of MOSQWell transistor future building block for optical communication

A new type of silicon MOSFET transistor, coupling both electronic and optical properties, is developed in order to overcome the indirect silicon bandgap constraint, and to serve as a future light emitting device in NIR [0.8-2μm] range, as part of a new building block in integrated circuits allowing ultra-high speed processors. Such QW structure enables discrete energy levels for light emission. Model and simulations are presented.

Anomalous Kink Effect in Low-Dimensional Gate-Recessed Fully Depleted SOI MOSFET at Low Temperature

Nanoscale MOSFETs Gate-Recessed Channel (GRC) device with a silicon channel thickness (tSI) as low as 2.2 nm was first tested at room temperature for functionality check, and then tested at low temperature (77 K) for I–V characterizations. In spite of its FD-SOI nanoscale thickness, the GRC device has surprisingly exhibited a Kink Effect in the output characteristics at 77 K. The anomalous Kink Effect can be explained by the increase of the lateral electric field in the drain junction with the channel extension zone when lowering the temperature.

Y-Function Analysis of the Low Temperature Behavior of Ultrathin Film FD SOI MOSFETs

The respective transfer characteristics of the ultrathin body (UTB) and gate recessed channel (GRC) device, sharing same W/L ratio but having a channel thickness of 46 nm, and 2.2 nm respectively, were measured at 300 K and at 77 K. By decreasing the temperature we found that the electrical behaviors of these devices were radically opposite: if for UTB device, the conductivity was increased, the opposite effect was observed for GRC. The low field electron mobility and series resistance values were extracted using a method based on Y-function for both the temperatures. If low values were found for UTB, very high values (g1) were extracted for GRC. Surprisingly, for the last device, the effective field mobility is found very low (l1) and is decreasing by lowering the temperature. After having discussed the limits of this analysis.This case study illustrates the advantage of the Y-analysis in discriminating a parameter of great relevance for nanoscale devices and gives a coherent interpretation of an anomalous electrical behavior.

Influence of Series Massive Resistance on Capacitance and Conductance Characteristics in Gate-Recessed Nanoscale SOI MOSFETs

Ultrathin body (UTB) and nanoscale body (NSB) SOI MOSFET devices, having a channel thickness ranging from 46 nm (UTB scale) down to 1.6 nm (NSB scale), were fabricated using a selective “gate recessed” process on the same silicon wafer. The gate-to-channel capacitance and conductance complementary characteristics, measured for NSB devices, were found to be radically different from those measured for UTBS. Consistent and trends are observed by varying the frequency , the channel length , and the channel thickness (). In this paper, we show that these trends can be analytically modeled by a massive series resistance depending on the gate voltage and on the channel thickness. The effects of leakage conductance and interface trap density are also modeled. This modeling approach may be useful to analyze and/or simulate electrical behavior of nanodevices in which series resistance is of a great concern.

Nanoscale silicon truncated conical photodetector at subwavelength aperture for NSOM applications

Silicon-based photodetector sharing subwavelength aperture and shaped as a truncated conical-probe, has been electrically and optically simulated. Designed for NSOM, it may collect near-field surface information with clear advantage of a resolution inaccessible by conventional optical microscopy. Results present a promising device for several wavelengths.