Awais M. Kamboh

A Scalable Wavelet Transform VLSI Architecture for Real-Time Signal Processing in High-Density Intra-Cortical Implants

This paper describes an area and power-efficient VLSI approach for implementing the discrete wavelet transform on streaming multielectrode neurophysiological data in real time. The VLSI implementation is based on the lifting scheme for wavelet computation using the symmlet4 basis with quantized coefficients and integer fixed-point data precision to minimize hardware demands. The proposed design is driven by the need to compress neural signals recorded with high-density microelectrode arrays implanted in the cortex prior to data telemetry. Our results indicate that signal integrity is not compromised by quantization down to 5-bit filter coefficient and 10-bit data precision at intermediate stages. Furthermore, results from analog simulation and modeling show that a hardware-minimized computational core executing filter steps sequentially is advantageous over the pipeline approach commonly used in DWT implementations. The design is compared to that of a B-spline approach that minimizes the number of multipliers at the expense of increasing the number of adders. The performance demonstrates that in vivo real-time DWT computation is feasible prior to data telemetry, permitting large savings in bandwidth requirements and communication costs given the severe limitations on size, energy consumption and power dissipation of an implantable device.

Area-Power Efficient VLSI Implementation of Multichannel DWT for Data Compression in Implantable Neuroprosthetics

Time-frequency domain signal processing of neural recordings, from high-density microelectrode arrays implanted in the cortex, is highly desired to ease the bandwidth bottleneck associated with data transfer to extra-cranial processing units. Because of its energy compactness features, discrete wavelet transform (DWT) has been shown to provide efficient data compression for neural records without compromising the information content. This paper describes an area-power minimized hardware implementation of the lifting scheme for multilevel, multichannel DWT with quantized filter coefficients and integer computation. Performance tradeoffs and key design decisions for implantable neuroprosthetics are presented. A 32-channel 4-level version of the circuit has been custom designed in 0.18-mum CMOS and occupies only 0.22 mm2 area and consumes 76 muW of power, making it highly suitable for implantable neural interface applications requiring wireless data transfer.

Computationally Efficient Neural Feature Extraction for Spike Sorting in Implantable High-Density Recording Systems

Modern microelectrode arrays acquire neural signals from hundreds of neurons in parallel that are subsequently processed for spike sorting. It is important to identify, extract, and transmit appropriate features that allow accurate spike sorting while using minimum computational resources. This paper describes a new set of spike sorting features, explicitly framed to be computationally efficient and shown to outperform principal component analysis (PCA)-based spike sorting. A hardware friendly architecture, feasible for implantation, is also presented for detecting neural spikes and extracting features to be transmitted for off chip spike classification. The proposed feature set does not require any off-chip training, and requires about 5% of computations as compared to the PCA-based features for the same classification accuracy, tested for spike trains with a broad range of signal-to-noise ratio. Our simulations show a reduction of required bandwidth to about 2% of original data rate, with an average classification accuracy of greater than 94% at a typical signal to noise ratio of 5 dB.

Resource constrained VLSI architecture for implantable neural data compression systems

Neural recordings from high-density microelectrode arrays implanted in the cortex require time-frequency domain processing to alleviate the data telemetry bottlenecks of bandwidth and power. Our previous work has shown that the energy compaction capability of the Discrete Wavelet Transform (DWT) offers a practical data compression solution that faithfully preserves the information in the neural signals. This paper presents a complete compression system including both lossy and lossless compression schemes, namely the DWT and Run Length Encoding. Performance tradeoffs and key design decisions for implantable applications are analyzed. A 32-channel, 4-level version of the circuit is presented. Custom designed in 0.5µm CMOS, occupying only 5.75mm2 and consuming 3mW of power (95µW per channel at 25Ks/sec), the implantable compression circuit is well suited for intra-cortical neural interface applications.

Adaptive threshold spike detection using stationary wavelet transform for neural recording implants

Spike detection is an essential first step in the analysis of neural recording signals. A new spike detection hardware architecture combining absolute threshold method and stationary wavelet transform (SWT) is described. The method enables spike detection with 90% accuracy even when the signal-to-noise is −1dB. A noise monitoring block was implemented to automatically calculate the appropriate threshold value for spike detection, and the system then chooses either absolute threshold method or the SWT method to optimize power consumption. The system was designed in 130nm CMOS and shown to occupy 0.082 mm2 and dissipate 0.45 μW for one channel.

Adaptive Threshold Neural Spike Detector Using Stationary Wavelet Transform in CMOS

Spike detection is an essential first step in the analysis of neural recordings. Detection at the frontend eases the bandwidth requirement for wireless data transfer of multichannel recordings to extra-cranial processing units. In this work, a low power digital integrated spike detector based on the lifting stationary wavelet transform is presented and developed. By monitoring the standard deviation of wavelet coefficients, the proposed detector can adaptively set a threshold value online for each channel independently without requiring user intervention. A prototype 16-channel spike detector was designed and tested in an FPGA. The method enables spike detection with nearly 90% accuracy even when the signal-to-noise ratio is as low as 2. The design was mapped to 130 nm CMOS technology and shown to occupy 0.014 mm2 of area and dissipate 1.7 μW of power per channel, making it suitable for implantable multichannel neural recording systems.

Analysis of Lifting and B-Spline DWT Implementations for Implantable Neuroprosthetics

The large amount of data generated by neuroprosthetic devices requires a high communication bandwidth for extra-cranial transmission, critically limiting the number and utility of wireless implantable applications. Discrete wavelet transform (DWT) can provide exceptionally efficient data compression for neural records. Two energy efficient hardware implementations for one dimensional, multi-level, multi-channel DWT have been compared to identify the optimal approach for real time processing within an implanted device. This paper defines area-power minimized hardware implementation of the lifting and B-spline DWT schemes and analyzes their performance tradeoffs for implantable neuroprosthetics. The lifting scheme is shown to be increasingly superior for a larger number of input channels.

Hardware architecture for on-chip unsupervised online neural spike sorting

Microelectrode arrays can acquire neural signals in parallel from multiple channels. Spike sorting has emerged as one of the most significant challenges in multichannel systems. An ideal spike sorting system must be implantable, unsupervised, online and scalable to hundreds of channels. This paper proposes a novel hardware architecture for on-chip and unsupervised neural spike sorting with Teager Energy Operator detection, Zero-Crossing Features and an online clustering algorithm, MCK Classifier, which is a modification of the standard K-Means. The reported classifier gives an average detection-classification accuracy of 82% at typical SNR of 7dB, which is within 2% of the standard K-Means classifier.

Design of a configurable neural Data compression system for intra-cortical implants

Multi-channel neural signal recordings need high data compression and efficient data transmission. Our previous work has shown a practical data compression solution based on discrete wavelet transform, multi-level thresholding and run length encoding. This paper presents a custom designed communication protocol for bidirectional data telemetry to and from the implanted module. A global controller is also presented which configures, operates and unites all the modules together effectively and efficiently into a 32-channel system. Performance of the communication protocol and the compression engine is analyzed.

Comparison of Lifting and B-spline DWT Implementations for Implantable Neuroprosthetics

The discrete wavelet transform (DWT) has been shown to provide exceptionally efficient data compression for neural records. This paper describes area-power minimized hardware implementations of the lifting and B-spline DWT schemes for multi-level, multi-channel DWT and analyzes their performance tradeoffs for implantable neuroprosthetics. The lifting scheme is shown to be increasingly superior for a larger number of input channels.