Axel Erlebach

Comparative Simulation Study of the Different Sources of Statistical Variability in Contemporary Floating-Gate Nonvolatile Memory

For the first time, a comprehensive comparative study of the impact of different sources of statistical variability in nonvolatile memory (NVM) has been carried out using the 3-D numerical simulation of large statistical ensembles and approaches based on the impedance-field method. Results of the threshold voltage variability in a template 32-nm floating-gate NVM subject to random discrete dopants (RDD), line edge roughness, oxide thickness fluctuations, polysilicon granularity, and interface trapped charge (ITC) are presented. The relative impact of each source of statistical variability has been highlighted, with RDD being identified as the dominant source and ITC as the next most dominant source. Based on the simulation of statistical samples of 1000 microscopically different devices, the shape and spread of the statistical distribution associated with each individual and combined sources of variability have been found to significantly be different from a normal distribution, particularly within the tails that may have significant implications for design and yield. Finally, an ensemble of 59 000 devices is used to characterize the combined impact of all sources of variability.

Scaling of Bulk pMOSFETs: (110) Surface Orientation Versus Uniaxial Compressive Stress

Six-band kmiddotp Monte Carlo device simulation is used to estimate the drain current enhancements in (110) surface and in uniaxially compressively stressed bulk pMOSFETs for gate lengths down to 30 nm. Satisfactory agreement is found with measured long-channel mobility enhancements as a function of the channel direction for (110) surface orientation or as a function of stress. It turns out that the stress-induced current improvement becomes larger than for the unstrained-Si (110) surface orientation at stress levels above 1 GPa. Specifically, for a gate length of 45 nm, the on-current enhancement is 50% for 1.5 GPa compared to 35% for the favorable lang-110rang channel direction in a (110) pMOSFET

TCAD methodology for simulation of GaN-HEMT power devices

Gallium nitride (GaN) based High Electron Mobility Transistors (HEMTs) are candidates for the next generation of power electronic devices and are therefore subject of intense research activities worldwide. Technology CAD (TCAD) has proven a major impact on the optimization of silicon based device technologies. It is a logical follow up to provide accurate simulation tools, methods and models for GaN-based device technologies that are benchmarked against hardware data. This work presents a systematic investigation of GaN-HEMTs by TCAD, including process emulation, in plane and full stress simulation, and drift-diffusion device simulation.

Hole Mobility Model With Silicon Inversion Layer Symmetry and Stress-Dependent Piezoconductance Coefficients

A model for stress-induced effective hole mobility enhancement in ¿110¿/(001) bulk pMOSFETs is presented. The model is based on first- and second-order stress-dependent piezoconductance coefficients and considers the symmetry reduction compared to bulk silicon induced by surface scattering at the gate interface. The piezoconductance coefficients are determined by Monte Carlo (MC) device simulation for five particular stress configurations with a maximum stress level of 3 GPa. Finally, comparisons between MC simulations and the new mobility model for general stress configurations show a good agreement thus validating the new approach.

Monte Carlo Stress Engineering of Scaled (110) and (100) Bulk pMOSFETs

Bulk pMOSFET performance enhancement by combinations of SiGe pockets, compressively stressed cap liner and (110) surface orientation is investigated by mechanical stress and Monte Carlo device simulation. In agreement with recent measurements, the on-current gain by a (110) surface orientation of the 45 nm pMOSFET with a 3 GPa compressive cap liner is 32% and 16% without and with the presence of Si0.8Ge0.2 pockets, respectively. However, the performance enhancement by a (110) surface orientation strongly decreases upon scaling and for increasing liner stress. This suggests that the enhanced mobility for (110) surface orientation may lose its advantage in the limit of further scaling and increasing stress.

Monte Carlo Simulation of the Performance Dependence on Surface and Channel Orientation in Scaled pFinFETs

Full-band Monte Carlo simulations are performed for FinFETs with gate lengths from 50 nm down to 10 nm comparing the improvement of (110) surface pFinFETs with channel directions in lang-110rang, lang-111rang and lang001rang to the results of the standard (001)/ lang110rang CMOS configuration. Due to the reduced importance of surface scattering in (a) the undoped pFinFET channel and (b) the short-channel regime the advantage of the (110) surface orientation in long-channel bulk pMOSFETs vanishes in the scaling limit, while the (001) channel direction becomes more beneficial. Consequently, our device simulation analysis suggests that a (-110) wafer with (110)/lang001rang pFinFETs and (00-l)/lang001rang nFinFETs is superior to a (00-1) wafer with (110)/ lang-100rang pFinFETs and (010)/lang-100rang nFinFETs in the ultrashort-channel regime

Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs

The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM). The calibration method for the stress-induced channel mobility and the external resistance is proposed using Ron-Lgate measurements of 32nm-node devices with different gate-pitches. The significant performance degradation due to simple gate-pitch scaling is predicted for 20nm-node technology with sub-100nm gate-pitch.

FinFET stress engineering using 3D mechanical stress and 2D Monte Carlo device simulation

A simulation methodology for FinFET stress and crystallographic orientation engineering is introduced and applied to tall scaled p- and n-type FinFETs with strained nitride layers on (001) wafers. The methodology consists of combining 3D mechanical stress simulation with 2D Monte Carlo device simulation where an averaged channel stress tensor is used. 50 nm down to 10 nm gate-length p- and n-type FinFETs with (110)/110 surface and channel orientation as well as (010)/100 n-type FinFETs are simulated with compressively and tensile strained cap layers, respectively, where liner stress values from 0.8 to 2.0 GPa are considered. Stress-induced Idsat gains in the range of 10 to 35% are found for pFinFETs with increasing tendency upon scaling, while the nFinFETs involve gains between 5 and 15% decreasing for smaller gate lengths with the highest absolute current being obtained for the 100 channel direction.

Layer Thickness and Stress-Dependent Correction for InGaAs Low-Field Mobility in TCAD Applications

A layer thickness and stress-dependent correction for InGaAs low-field mobility in technology computer-aided design applications is presented. This correction is based on a simplified phonon-limited mobility, which accounts for the geometrical quantization and stress effects. The stress effect is modeled with a linear deformation potential model for the valley energy change and a stress-related change of the effective mass and nonparabolicity of Γ valley. The model shows good agreement with known literature data for the dependence of the In0.53Ga0.47As mobility in double-gate structures on the layer thickness. Simulation results for the stress dependence of the mobility in In1-xGaxAs devices are also presented.

New implantation tables for B, BF 2 , P, As, In and Sb

After implantation, the distribution of ions can be described by analytical functions with parameters depending on implantation conditions. In this work, a calibrated Monte Carlo simulator was used to calculate tables for the implantation of B, BF2, P, As, In and Sb. Starting from systematic Monte Carlo data we extracted the parameters of two Pearson functions for dopant profiles in crystalline silicon and single Pearson functions for profiles in SiO2, Si3N4 and poly-silicon. The new tables cover more dopant species and implantation conditions than existing implantation tables and provide excellent agreement with 90 SIMS profiles. In a 2D nMOS test case, the implantation simulation with the new tables provides the same accuracy as Monte Carlo simulations.