Ayan Mandal

Influence of beneficial microorganisms during in vivo acclimatization of in vitro-derived tea (Camellia sinensis) plants

The effects of native isolates of Pseudomonas fluorescens, Azospirillum brasilense, and Trichoderma harzianum on rooting and acclimatization of in vitro-grown shoots and plantlets of tea were evaluated. In vitro bacterization of P. fluorescens failed to establish, while both T. harzianum and A. brasilense retarded shoot growth, eventually overtaking shoot cultures in in vitro rooting. Acclimatization of rooted plantlets in soil amended with bioinoculants, either individually or in various combinations, promoted plantlet survival. Moreover, efficiency of nutrient uptake of plantlets was higher in the presence of microorganisms. Root rot or wilting of tissue culture-derived plants was not observed in bioinoculant-treated plants, as they possessed relatively higher activities of defense enzymes, including peroxidase and phenylalanine ammonia lyase.

A Hardware Scheduler for Real Time Multiprocessor System on Chip

This paper presents the design and implementation of a low-power hardware scheduler for multiprocessor system-on-chips. The Pfair scheduling algorithm is considered with three different implementation schemes: replicated software scheduler running on each processor, single software scheduler running on a dedicated processor and the proposed hardware scheduler. Experimental evaluation with benchmarks shows that the hardware scheduler outperforms the other two schemes in terms of energy consumption by an order of magnitude of 10^5 and scheduling delay by an order of magnitude of 10^3.

Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits

Standing wave oscillators (SWOs) are attractive since they can sustain extremely high oscillation frequencies with very low power consumption due to their resonant nature. In this paper, we present a technique to design a high frequency SWO to cover a large area on an IC. We achieve this by combining two techniques. The first technique increases the area coverage of an individual SWO by ensuring that it sustains an odd number (greater than one) of standing waves along the ring. The second approach further increases the area coverage by tiling multiple SWOs side by side, and connecting them such that they oscillate with the same high frequency and phase. The combined approach is simulated for a 3×3 array of tiles, using 3D, skin-effect adjusted RLC parasitic extraction. Our simulations are performed using a 90nm process, and indicate that this tiled structure can oscillate at about 7.25 GHz, with low power (about 68 mW per SWO tile) and low jitter (about 3.1% of the nominal clock period).

A fast, source-synchronous ring-based network-on-chip design

Most network-on-chip (NoC) architectures are based on a mesh-based interconnection structure. In this paper, we present a new NoC architecture, which relies on source synchronous data transfer over a ring. The source synchronous ring data is clocked by a resonant clock, which operates significantly faster than individual processors that are served by the ring. This allows us to significantly improve the cross section bandwidth and the latency of the NoC. We have validated the design using a 22 nm predictive process. Compared to the state-of-the-art mesh based NoC, our scheme achieves a 4.5× better bandwidth, 7.4× better contention free latency with 11% lower area and 35% lower power.

Penile metastasis secondary to bladder cancer: A report of two cases

Penile metastasis secondary to primary bladder cancer is a rare entity and represents a challenging problem. The common mode of spread to the penis is by retrograde venous route. The overall outcome is dismal and most patients will die within 1 year even after optimum treatment. Here, we report two such cases.

Boolean satisfiability using noise based logic

Noise-based Logic (NBL) is a probabilistic logic system which can be used to simultaneously apply a superposition of arbitrarily many input vectors to a SAT instance. Using this property, we can determine whether an instance is SAT in a single operation. A satisfying solution can be found by iteratively performing SAT checks up to n times, where n is the number of variables in the SAT instance. In this paper, we formulate NBL-based SAT, and discuss its scalability. The NBL-based SAT engine has been simulated in software for validation purposes, although the focus of the paper is on the theory of NBL-based SAT.

Exploring topologies for source-synchronous ring-based network-on-chip

The mesh interconnection network has been preferred by the Network-on-Chip (NoC) community due to its simple implementation, high bandwidth and overall scalability. Most existing mesh-based NoC designs operate the mesh at the same or lower clock speed as the processing elements (PEs). Recently, a new source synchronous ring-based NoC architecture has been proposed, which runs significantly faster than the PEs and offers a significantly higher bandwidth and lower communication latency. The authors implement the NoC topology as a mesh of rings, which occupies the same area as that of a mesh. In this work, we evaluate two alternate source synchronous ring-based NoC topologies called the ring of stars (ROS) and the spine with rings (SWR), which occupy a much lower area, and are able to provide better performance in terms of communication latency compared to a state of the art mesh. In our proposed topologies, the clock and the data NoC are routed in parallel, yielding a fast, synchronous, robust design. Our design allows the PEs to extract a low jitter clock from the high speed ring clock by division. The area and performance of these ring-based NoC topologies is quantified. Experimental results on synthetic traffic show that the new ring-based NoC designs can provide significantly lower latency (upto 4.6×) compared to a state of the art mesh. The proposed floorplan-friendly topologies use fewer buffers (upto 50% less) and lower wire length (upto 64.3% lower) compared to the mesh. Depending on the performance and the area desired, a NoC designer can select among the topologies presented.

A low-jitter phase-locked resonant clock generation and distribution scheme

Clock distribution networks have traditionally been optimized to minimize end-to-end delay of the distribution network. However, since most digital ICs have an on-chip PLL, a more relevant design goal is to minimize cycle-to-cycle jitter. In this paper, we present a novel low-jitter phase-locked clock generation and distribution methodology which uses resonant standing wave oscillators (SWOs). In contrast to traveling wave oscillator rings (TWOs or “rotary” clocks), our SWO achieves the same phase at every point in the ring, making it amenable to a synchronous design methodology. The standing wave oscillator is controlled by coarse as well as fine tuning. Coarse tuning is achieved by varying the ring inductance, while fine tuning is accomplished by varying the ring capacitance. Clock distribution is done by routing the resonant ring chip-wide in a “comb” like manner. Experimental results demonstrate that the cycle-to-cycle jitter and skew of our approach is dramatically lower than existing schemes, while the power consumption is significantly lower as well. These benefits occur due to the resonant nature of our SWO-based clock generation and distribution approach.

An Automated Approach for Minimum Jitter Buffered H-Tree Construction

In recent fabrication technologies, buffered clock distribution networks have become increasingly popular due to increasing on-chip wiring delays. Traditionally, clock distribution networks has been optimized to minimize end-to-end skew of the distribution network. However, since most ICs have an on-chip PLL, we argue that the design goal of minimizing end-to-end jitter is more relevant. In this paper, we present a dynamic programming based approach to synthesize a minimum cost buffered H-tree clock distribution network. Our cost functions are a weighted sum of power and jitter, and a weighted sum of power and end-to-end delay of the distribution network. Our approach is based on precharacterizing the delay, jitter and power of buffered segments of different lengths, topologies, buffer sizes and wire-codes. Using this information, a dynamic programming (DP) engine automatically generates the optimal H-tree that minimizes the appropriate cost function. Compared to a manually constructed buffered H-tree network, our approaches are able to reduce both jitter (by as much as 28%, and power by as much as 46%. When optimizing for minimum jitter, the DP engine generates a H-tree with lower jitter than when optimizing for minimum delay, thereby validating our approach, and proving its usefulness.

Fast On-Chip Data Transfer Using Sinusoid Signals

In Chapter 2, we demonstrate that resonant clocking can be used as an ultra high-speed, low-jitter, low-power, stable on-chip clock generation and distribution scheme. In Chapter 3, we use such a clock to design a high speed source-synchronous ring-based NoC architecture. This helped us achieve inter-processor communication with minimal latency. In this chapter, we investigate an alternate design for high speed on-chip data transfer, which utilizes resonant oscillators. Traditional (pulse-based) on-chip data transfer achieves a maximum data transfer rate of one bit per wire per clock cycle. In this work, we explore the use of sinusoidal signals (generated using SWOs) of different frequencies as information carriers for on-chip data transfer. The advantage of our method is the ability to superimpose such sinusoids and thereby effectively send multiple logic values along the same wire in a clock cycle. Initial experimental results show that for the same throughput as a traditional scheme, we require 50 % fewer wires. This technique can be employed for off-chip data transfer as well.