Aydin Carus

Multi-pipelined and memory-efficient packet classification engines on FPGAs

A packet classification task incorporated in network firewalls to recognize and sift threats or unauthorized network accesses is accomplished by checking incoming packet headers against a pre-defined filter set. Plenty of solutions to reduce the memory requirement of filter set storage and accommodate packet classification to line rates have been proposed over the past decade. Among all the existing approaches, hierarchical data structures maintain great memory performance however their hardware realization suffers from two issues: (i) backtracking and (ii) memory inefficiency. In this paper, we propose two data structures denoted range tree-linked list hierarchical search structure (RLHS) and value-coded trie structure with -branch property (VC) for packet classification. RLHS resolves backtracking by exploiting range tree in Stage 1 and linked list data structure in Stage 2 overcomes the memory inefficiency. VC trie that naturally does not involve backtracking problem, solves memory inefficiency issue by comprising a fixed size bin at each node. Apart from conventional binary trie, a new rule is inserted into the first available bin on the path of this rule in a VC trie, and -branch property is utilized in case all the bins are full. We also propose a rule categorization algorithm that partitions an input ruleset by considering the field features of rules to minimize the memory requirement. To support the proposed data structures, we designed high throughput SRAM-based parallel and pipelined architectures on Field Programmable Gate Arrays (FPGAs).

Large-scale SRAM-based IP lookup architectures using compact trie search structures

Display Omitted We proposed two compact data structures for Internet Protocol (IP) lookup.The node size variety leads to the memory inefficiency in hardware implementations.Compact Trie Forest (CTF) uses multiple disjoint pipelines to solve the problem.Compact Trie? (CT?) splits nodes into sequentially connected multiple small nodes.To support each data structure, two pipelined SRAM-based architectures are proposed. SRAM-based pipelined architectures for high-speed IP lookup using Field Programmable Gate Arrays (FPGAs) has recently attracted a great deal of attention from researchers. Due to the limited amount of on-chip memory and the number of I/O pins of FPGAs, compact data structures providing high memory efficiency are in great demand.In IP lookup, a binary trie that is an ordered tree data structure is used to store the routing table entries. In this paper, we propose two compact trie structures denoted Compact Trie Forest (CTF) and Compact Trie? (CT?) for Internet Protocol (IP) lookup. The large variant in node sizes leading to the memory inefficiency in hardware implementation is resolved by using multiple disjoint pipelines in CTF. CT? solves the problem within a single pipeline by splitting large nodes into sequentially connected multiple small and fixed size nodes. To support each data structure, two pipelined SRAM-based architectures optimized by allowing multiple memory banks in each stage are also proposed.

Range tree-linked list hierarchical search structure for packet classification on FPGAs

Field Programmable Gate Arrays (FPGAs) satisfying the abundant parallelism and high operating frequency demands are the most promising platform to realize SRAM-based pipelined architectures for high-speed packet classification. Due to the restrictions of the state-of-the-art FPGAs on the number of I/O pins and on-chip memory, larger filter databases can hardly be accommodated by the current approaches. Therefore, new data structures which are frugal with the memory are lately in high demand. In this paper, two stage range tree-linked list hierarchical search structure (RLHS) is introduced for packet classification. Our proposed structure comprising range tree in Stage 1 and linked lists in Stage 2, resolves backtracking and memory inefficiency problems in the pipelined hardware implementation of hierarchical search structures. We further present a categorization algorithm that partitions an input ruleset based on the field characteristics of rules to reduce the memory requirement. Each partition has an individual RLHS with specialized node structures free from redundant fields used for storing wildcards and range points. Our design is realized on an SRAM-based parallel and pipelined architecture using FPGAs to achieve high throughput. Utilizing a state-of-the-art FPGA, RLHS architecture can sustain a 404 million packets per second throughput or 129 Gbps (for the minimum packet size of 40 Bytes) while maintaining packet input order and supporting in-place non-blocking rule updates.

Compact trie forest: Scalable architecture for IP lookup on FPGAs

Memory efficiency with compact data structures for Internet Protocol (IP) lookup has recently regained much interest in the research community. In this paper, we revisit the classic trie-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. Among all existing implementation platforms, Field Programmable Gate Array (FPGA) is a prevailing platform to implement SRAM-based pipelined architectures for high-speed IP lookup because of its abundant parallelism and other desirable features. However, due to the available on-chip memory and the number of I/O pins of FPGAs, state-of-the-art designs cannot support large routing tables consisting of over 350K prefixes in backbone routers. We propose a search algorithm and data structure denoted Compact Trie (CT) for IP lookup. Our algorithm demonstrates a substantial reduction in the memory footprint compared with the state-of-the-art solutions. A parallel architecture on FPGAs, named Compact Trie Forest (CTF), is introduced to support the data structure. Along with pipelining techniques, our optimized architecture also employs multiple memory banks in each stage to further reduce memory and resource redundancy. Implementation on a state-of-the-art FPGA device shows that the proposed architecture can support large routing tables consisting up to 703K IPv4 or 418K IPv6 prefixes. The post place-and-route result shows that our architecture can sustain a throughput of 420 million lookups per second (MLPS), or 135 Gbps for the minimum packet size of 40 Bytes. The result surpasses the worst-case 150 MLPS required by the standardized 100GbE line cards.

Performance comparison of JPEG, JPEG2000 & JPEG XR image compression standards

In this study, the performances of JPEG (the most widely used lossy image compression standard until it was published in 1992), JPEG2000 (designed to provide superior image quality at low bit rates) and JPEG XR (aimed to reach the speed of JPEG and the quality of JPEG2000) are evaluated with an application developed in C# language which is able to use different codecs. The results show that recently developed JPEG standard (JPEG XR) is able to compress images with the same quality as JPEG2000, but not the same speed as JPEG.

Clustered Linked List Forest for IPv6 Lookup

Providing a high operating frequency and abundant parallelism, Field Programmable Gate Arrays (FPGAs) are the most promising base to realize SRAM-based pipelined architectures for high-speed Internet Protocol (IP) lookup. Owing to the restrictions of the state-of-the-art FPGAs on the number of I/O pins and on-chip memory, the existing approaches can hardly accommodate the large and sparsely-distributed IPv6routing tables. Therefore, memory efficient data structures are recently in high demand. In this paper, clustered linked list forest(CLLF) data structure is proposed for solving the longest prefix matching (LPM) problem in IP lookup. Our structure comprising clustered multiple parallel linked lists achieves significant memory compaction in comparison to the existing approaches. CLLF data structure is implemented on a high throughput SRAM-based parallel and pipelined architecture on FPGAs. Utilizing a state of-the-art FPGA device, CLLF architecture can accommodate up to 712K IPv6 prefixes while supporting fast incremental routingtable updates.