Ayman A. Fayed

A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS

Implementing efficient and cost-effective power regulation schemes for battery-powered mixed-signal SoCs is a key focus in integrated circuit design. This paper presents a fully-integrated switched-capacitor DC-DC converter in 45 nm digital CMOS technology. The proposed implementation uses digital capacitance modulation instead of traditional PFM and PWM control methods to maintain regulation against load current changes. This technique preserves constant frequency switching while also scaling switching and bottom-plate losses with changes in load current. Therefore, high efficiency can be achieved across different load current levels while maintaining a predictable switching noise behavior. The converter occupies only 0.16 mm2, and operates from 1.8 V input. It delivers a programmable sub-1 V power supply with efficiency as high as 69% and load current between 100 μA and 8 mA. Measurement results confirm the theoretical basis of the proposed design.

A 0.16mm 2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS

Reducing power consumption through VDD scaling is a major trend in nanometer CMOS circuits. In modern wireless SoCs, multiple power domains operate below 1.2V and draw less than 10mA of current. Currently, these domains are powered from a 1.8V rail through a low drop-out linear regulator (LDO). The 1.8V rail is obtained from a Li-ion battery using a switching regulator with off-chip passives. It is highly inefficient to power circuit blocks that operate below 1.2V through LDOs. Switched-capacitor (SC) DC-DC converters are a viable solution to replace LDOs in some on-chip power domains but they currently occupy a large on-chip area [1]. Also, the voltage regulation schemes employed by current SC converters are either unsuitable in wireless systems or do not provide high efficiencies in on-chip use cases due to the dominance of bottom-plate and switching losses [2]. In this paper, a completely on-chip SC DC-DC converter that uses a digital capacitance modulation scheme to achieve voltage regulation is presented. The converter occupies only 0.16mm2 in total area and provides up to 8mA of current to output voltages between 0.8V to 1V from a 1.8V input while switching at 30MHz.

A low-voltage, highly linear voltage-controlled transconductor

A low-voltage fully differential, voltage-controlled transconductor is described. The proposed transconductor achieves a wide input/control voltage range, with a highly linear transconductance factor and truly fully differential output currents. The transconductor is used to implement a G/sub m/-C adaptive forward equalizer (FE) for a 125 Mbps wire line transceiver using digital core transistors with channel length of no more than double the feature size in a typical digital CMOS 180-nm process and supply voltage as low as 1.6 V. The adaptive FE enables IEEE 1394b transceivers to operate over UTP-5 cables for up to 100 m in length. The transconductor stage occupies 1945 /spl mu/m/sup 2/ and consumes an average power of 418 /spl mu/w at 125 Mbps and 1.8-V supply.

A Low-Voltage Low-Power CMOS Analog Adaptive Equalizer for UTP-5 Cables

An analog adaptive equalizer based on a feed-forward architecture is implemented in 0.18-mum digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125 Mbps over unshielded-twisted-pair category-5 cable of up to 100 m. Novel low-power circuit and system techniques resulted in 3.7-mW total power consumption and supply voltage operation as low as 1.6 V. The maximum peak-to-peak jitter at the output of the equalizer (including the transmit path driver) under all cable length is 0.33 UI. The total area of the equalizer is 27738 mum2.

Spurious-noise-free buck regulator for direct powering of analog/RF loads using PWM control with random frequency hopping and random phase chopping

Buck regulators are widely employed in portable devices due to their high power-conversion efficiency. However, due to their spurious output noise, they are not directly used to power sensitive analog/RF modules, and subsequent linear low-dropout regulators (LDOs) are needed to generate secondary low-noise supply rails for these modules. This results in lower efficiency, and increased size and cost. Moreover, as switching frequencies increase to reduce passive components, LDOs become less effective in filtering the switching noise due to their poor power-supply rejection (PSR) beyond 1MHz [1]. Several techniques for reducing the spurious noise of buck regulators by manipulating their switching behavior have been studied. This includes using ΔΣ or Δ modulators in the control loop [2, 3], which although reduce the spurs, result in large increases in the noise floor that mandates subsequent LDOs [1]. Other techniques redistribute the power of each spur into multiple smaller ones using random frequency hopping [4], or periodic monotonic frequency stepping [5]. However, the resulting spectrum continues to be spurious and the reduction reported in the largest spur is limited to 10 to 12dB. This limited reduction, coupled with the fact that many extra spurs are generated, leaves the load circuitry vulnerable to performance degradation. This paper proposes a pulse-width modulation (PWM) control scheme for buck converters based on combining random frequency hopping with phase chopping. The technique results in full elimination of spurs, elimination of hopping transients, very low noise floor, and minimalist implementation with little overhead on area and power.

PWM Control Architecture With Constant Cycle Frequency Hopping and Phase Chopping for Spur-Free Operation in Buck Regulators

This paper introduces a new Pulse-Width Modulation (PWM) control scheme for buck regulators that combines phase chopping with frequency hopping to achieve spur-free operation while delivering low output noise floor with no subharmonics due to hopping. The proposed regulator hops between two, four, or eight switching frequencies, but chops their phases to fully eliminate spurs, even with only two frequencies. Peaking in the noise floor around the eliminated spurs is minimized by hopping as fast as every switching cycle, and by spacing the frequencies 0.5 MHz apart. This results in less than 1.7% drop in the regulators efficiency and less than 4 mV increase in the voltage ripple. Implemented in standard 0.35- μm CMOS technology, the proposed regulators area and power overhead beyond conventional single-switching-frequency design is only 8% and 3%, respectively. With a spur-free spectrum and low noise floor across all frequencies, the proposed architecture can serve as a low-noise regulator for powering noise-sensitive loads without post linear regulation or additional passive filtering. Moreover, spur-free operation facilitates its integration in mixed-signal systems on chip without interfering with sensitive circuits that share the same substrate or power rails. The proposed architecture is also a good candidate for implementing class-D amplifiers, as it preserves the control loops linearity.

A feasibility study of high-frequency buck regulators in nanometer CMOS technologies

The feasibility of implementing buck converters with switching frequencies of 200MHz and beyond to reduce the size of passive components to integrate-able levels is investigated. Switching losses at such high frequencies are compared to traditional converters implemented on typical analog power technologies to demonstrate that the scaling down of CMOS technologies to nanometer levels can indeed enable switching at such high frequencies while maintaining decent efficiency. Preliminary simulation results on a typical 45nm technology are used to verify the feasibility.

A Low-Noise PFM-Controlled Buck Converter for Low-Power Applications

APFM-controlled buck converter with discrete frequency hopping is proposed. The converter employs two uniquely related switching frequencies to fully spread the converters output switching noise without generating additional tones at any of the switching frequencies. The peaking in the noise floor resulting from spreading the switching noise is reduced by using up to eight switching frequencies. The converter is implemented in 0.35 μm standard CMOS technology and occupies 0.29 mm2. With a spur-free output spectrum and low noise floor peaking, the proposed converter is ideal for low-current noise-sensitive loads such as analog and RF circuit loads in portable communication devices.

A Buck Converter With Reduced Output Spurs Using Asynchronous Frequency Hopping

A frequency-hopped buck converter with reduced output spurs in 0.35-μm CMOS is presented. The converter uses pulsewidth-modulation control with eight switching frequencies to achieve 13.2-dB reduction in output spurs from the traditional single-frequency case. The proposed implementation maintains the continuity of the ramp signal, regardless of the frequency selected or when it is selected. Therefore, the hopping rate can be set independently using a clock that is asynchronous to the internal switching frequencies of the converter, and no synchronization between the switching frequencies themselves or between them and the hopping clock is necessary. Moreover, the proposed continuous ramp signal minimizes transients associated with hopping, hence maximizing the hopping rate and spur reduction.

A GSM Power Amplifier Directly-Powered From a DC-DC Power Converter

A commercial off-the-shelf GSM PA powered directly from a DC-DC converter is presented. The converter is implemented in 0.35 μm CMOS and employs frequency hopping with phase chopping to eliminate spurious noise. Measurement results demonstrate elimination of spurs, allowing an incompliant GSM PA that is violating the limits of the GSM spectral mask by 9.3 dB to be brought back to compliance without additional filtering or linear regulation between the converter and the PA.