B. R. Singh

Electrical characterization of the metal ferroelectric oxide semiconductor and metal ferroelectric nitride semiconductor gate stacks for ferroelectric field effect transistors

This paper presents our work on electrical characterization of metal-ferroelectric-oxide-semiconductor (MFeOS) and metal-ferroelectric-nitride-semiconductor (MFeNS) structures for nonvolatile memory applications. Thin films of lead zirconate titanate (PZT: 35:65) have been used as ferroelectric material on 2.5–5 nm thick thermally grown SiO2 and Si3N4 as buffer layer for MFeOS and MFeNS structures, respectively. Capacitance-Voltage (C-V) and Current-Voltage (I-V) characteristics were used for electrical characterization. Our comparative results reveal that the MFeNS structure with 2.5 nm thick buffer layer has higher memory window of about 3.6 V as compared to 3 V for similar MFeOS structure. Also superior electrical properties such as lower leakage current and higher dielectric strength were observed in MFeNS structures. Higher nitridation time was observed to deteriorate the polarization characteristics resulting in reduced memory window. The highest memory window of 6.5 V was observed for SiO2 buffer layer thickness of 5 nm. We also observed that the annealing temperature influences the leakage current characteristic and memory window of these structures.This paper presents our work on electrical characterization of metal-ferroelectric-oxide-semiconductor (MFeOS) and metal-ferroelectric-nitride-semiconductor (MFeNS) structures for nonvolatile memory applications. Thin films of lead zirconate titanate (PZT: 35:65) have been used as ferroelectric material on 2.5–5 nm thick thermally grown SiO2 and Si3N4 as buffer layer for MFeOS and MFeNS structures, respectively. Capacitance-Voltage (C-V) and Current-Voltage (I-V) characteristics were used for electrical characterization. Our comparative results reveal that the MFeNS structure with 2.5 nm thick buffer layer has higher memory window of about 3.6 V as compared to 3 V for similar MFeOS structure. Also superior electrical properties such as lower leakage current and higher dielectric strength were observed in MFeNS structures. Higher nitridation time was observed to deteriorate the polarization characteristics resulting in reduced memory window. The highest memory window of 6.5 V was observed for SiO2 buffer l...

High performance hardware implementation of AES using minimal resources

Increasing need of data protection in computer networks led to the development of several cryptographic algorithms hence sending data securely over a transmission link is critically important in many applications. Hardware implementation of cryptographic algorithms are physically secure than software implementations since outside attackers cannot modify them. In order to achieve higher performance in todays heavily loaded communication networks, hardware implementation is a wise choice in terms of better speed and reliability. This paper presents the hardware implementation of Advanced Encryption Standard (AES) algorithm using Xilinx-virtex 5 Field Programmable Gate Array (FPGA). In order to achieve higher speed and lesser area, Sub Byte operation, Inverse Sub Byte operation, Mix Column operation and Inverse Mix Column operations are designed as Look Up Tables (LUTs) and Read Only Memories (ROMs). This approach gives a throughput of 3.74Gbps utilizing only 1% of total slices in xc5vlx110t-3-ff1136 target device.

Radiation Induced Charge Trapping in Sputtered

The present paper deals with radiation induced charge trapping at reactively sputtered ZrO2/Si interface deposited in N2 containing plasma. MOS C-V and I-V techniques were used for interface characterization. Radiation induced degradation of sputtered high k dielectric (ZrO2)/Si interface was studied using Cu X-ray source. The devices were irradiated with x-rays at different doses ranging from 100 rad to 1 Mrad. Enhanced leakage current and shift in flat band voltage towards negative value was observed in annealed devices after exposure to radiation. The effect of post deposition annealing on the electrical behavior of ZrO2/Si interface was also investigated. The annealed devices showed better electrical and reliability characteristics. Different device parameters such as flat band voltage, leakage current, charge defects has been extracted. Nitrogen incorporated ZrO2 is found to improve the radiation hardness of the devices.

{\rm ZrO}_{\rm 2} \!\! : \!\! {\rm N}

ABSTRACT This paper describes the heavy ion-induced effects on the electrical characteristics of reactively sputtered ZrO2 and Al2O3 high-k gate oxides deposited in argon plus nitrogen containing plasma. Radiation-induced degradation of sputtered high-k dielectric ZrO2/Si and Al2O3/Si interface was studied using 45 MeV Li3+ ions. The devices were irradiated with Li3+ ions at various fluences ranging from 5 × 109 to 5 × 1012 ions/cm2. Capacitance–voltage and current–voltage characteristics were used for electrical characterization. Shift in flat band voltage towards negative value was observed in devices after exposure to ion radiation. Post-deposition annealing effect on the electrical behavior of high-k/Si interface was also investigated. The annealed devices showed better electrical and reliability characteristics. Different device parameters such as flat band voltage, leakage current, interface defect density and oxide-trapped charge have been extracted.The surface morphology and roughness values for films deposited in nitrogen containing plasma before and after ion radiation are extracted from Atomic Force Microscopy.

Dielectric Thin Films on Silicon

ABSTRACT We have investigated the electrical characteristics of Metal/Ferroelectric/High-k/Si capacitor structures using sputtered Lead-Zirconate-Titanate (Pb[Zr0.35Ti0.65]O3 or PZT) and HfO2 thin films as ferroelectric and high-k material respectively. C-V, I-V characterization has been carried out to investigate the memory window and the leakage characteristics. The dependence of the memory window and leakage current on the buffer layer thickness and device annealing temperature has been studied. X-Ray diffraction (XRD) data demonstrate crystallization of HfO2 film and increase in defects in the PZT film after N2 annealing in the temperature range of 600°C–700°C. The maximum memory window of 6.8 V is observed in the M/Fe/High-k/S structure with 8 nm buffer layer as compared to the 2.3 V in the M/Fe/S structure, annealed at the same temperature i.e. 500°C. This device is observed to be capable of handling the voltage of 38 V before breakdown as compared to the 17 V in M/Fe/S structure. The leakage current density of the order 10−6 A/cm2 is observed for the voltage sweep of +20 V.

Swift ion irradiation effect on high-k ZrO2- and Al2O3-based MOS devices

This paper describes the effect of ionizing radiation on the interface properties of Al/Ta2O5/Si metal oxide semiconductor (MOS) capacitors using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The devices were irradiated with X-rays at different doses ranging from 100 rad to 1 Mrad. The leakage behavior, which is an important parameter for memory applications of Al/Ta2O5/Si MOS capacitors, along with interface properties such as effective oxide charges and interface trap density with and without irradiation has been investigated. Lower accumulation capacitance and shift in flat band voltage toward negative value were observed in annealed devices after exposure to radiation. The increase in interfacial oxide layer thickness after irradiation was confirmed by Rutherford Back Scattering measurement. The effect of post-deposition annealing on the electrical behavior of Ta2O5 MOS capacitors was also investigated. Improved electrical and interface properties were obtained for samples deposited in N2 ambient. The density of interface trap states (Dit) at Ta2O5/Si interface sputtered in pure argon ambient was higher compared to samples reactively sputtered in nitrogen-containing plasma. Our results show that reactive sputtering in nitrogen-containing plasma is a promising approach to improve the radiation hardness of Ta2O5/Si MOS devices.

Lead-zirconate-titanate based metal/ferroelectric/high-K/semiconductor (M/Fe/High-K/S) gate stack for non-volatile memory applications

High speed analog to digital converters (ADC), memory sense amplifiers, RFID applications, data receivers with low power and area efficient designs has attracted a wide variety of dynamic comparators. This paper presents an improved design for a dynamic latch based comparator in achieving higher speed of conversion targeting 8-bit asynchronous successive approximation register (ASAR) ADC. The comparator has two different stages comprising of a dynamic differential input gain stage and an output latch. The objective of improving the speed of conversion is done by removing the dead time required for reset in the differential input stage. In the proposed work the output node in the differential gain stage requires lesser time to regain higher charge potential. The proposed methodology has been designed and simulated using 180nm CMOS technology operated on a single 1V power supply and achieves complete 8-bit conversion in 75nsec.

Ionizing radiation effects on electrical and reliability characteristics of sputtered Ta2O5/Si interface

The present paper deals with the design of single axis folded beam electro-statically actuated comb-drive based accelerometer for high resonant frequency range (1 MHz) application. The accelerometer design and analysis is carried out in accordance with standard SOI single mask technology using MEMS Pro v5.1 simulation tool.

An Improved Dynamic Latch Based Comparator for 8-Bit Asynchronous SAR ADC

A low power variable resolution analog-to-digital converter (ADC) architecture has been proposed in a 45-nm CMOS technology. The design uses only 6 comparators for achieving the required conversion and thus saves huge amount of area in comparison to conventional flash ADC (which requires 2n comparators for same bits). The proposed ADC when designed for 4 - 6 bits, exhibit a SNR of 35.9 dB and SNDR of 35.4 dB and achieves a maximum speed of 1.4 GS/s. The ADC dissipates 80 μW, 96 μW and 1.15 mW power for 4, 5 and 6 bits respectively.

Design and analysis of high resonant frequency (1 MHz) MEMS accelerometer

This short note presents the simulation result on the effect of channel engineering i.e., non-uniform channel doping on short channel effects (SCE) in nano Fin-FET devices using Silvaco TCAD tool. The nano Fin-FET structures were generated using DEVEDIT and the effect of channel doping concentration has been studied. The optimum doping concentration profile has been observed to considerably improve the SCE in general and drain induced barrier lowering (DIBL) in particular.