B. S. Premananda

Low Complexity Speech Enhancement Algorithm for Improved Perception in Mobile Devices

In mobile phones, perceived quality of speech signal deteriorates significantly in the presence of background noise since near-end/surrounding noise also arrives at the near-end listener’s ears. The quality of the received signal varies widely depending upon signal strength and unavoidable background noise in the user environment. There is a need to improve the quality of received speech signal in noisy conditions by developing the speech enhancement algorithms. This paper focuses on the impact of the various background noises on signal perception and mechanisms to mitigate the noise impact for improved signal perception. Gain adjustment process with simple time domain approach has been adapted to improve the quality and intelligibility of the speech signal in the noisy environments by automatically increasing output levels when the noise dominates. Since time domain approach has been used, it is less complex and consumes very less battery power of the mobile and also efficiently masks the background noise. This paper studies the effect of various signal parameters on automatic gain adjustment of the received signal to enhance its perception.

Speech enhancement to overcome the effect of near-end noise in mobile phones using psychoacoustics

In mobile phones, perceived quality of speech signal deteriorates significantly in the presence of near-end/surrounding noise as it arrives at the near-end listeners ears. There is a need to improve the intelligibility and quality of the received speech signal in noisy environments by developing speech enhancement algorithms. Paper focuses on the impact of near-end noises on signal degradation. Gain adjustment process employing psychoacoustic has been adopted to improve the intelligibility and quality of the speech signal in the noisy environments by automatically enhancing the speech signals when the noise dominates. Intelligibility and quality of enhanced speech signal are measured using SII and PESQ. Experimental results show intelligibility and quality improvement of speech signal with the proposed method over the unprocessed far-end speech signal. Approach is more efficient in overcoming the degradation of speech signals in presence of near-end noise.

Design and Development of High-speed Data Acquisition System with Cyclone FPGA

The use of an automated Data Acquisition System (DAS) is very important in testing and measurement systems. The desire is extremely high in the DAS with high speed, multi-channel, and large capacity, so research in this area becomes very significant. The growing problem in DAS is to acquire the data with the required data rate and store data onto the on-chip memory. Microcontroller, microprocessor or Digital Signal Processors (DSP) devices can be programmed as a DAS, but these devices comprise problems, such as slower data acquisition rates, nonavailability of sufficient on-chip memory, etc. To overcome these above drawbacks, this paper provides an approach to design and develop DAS based on the Field Programmable Gate Array (FPGA). To acquire the data from Analog to Digital Converter (ADC) to FPGA, an Inter Integrated Circuit (I2C) serial communication protocol is used. I2C master communication protocol is designed and developed using VHDL with the Quartus II version 13.1, and the I2C master protocol is implemented in cyclone III FPGA. FPGA is acting as a master controller. DAS with the FPGA will provide the better acquisition results compared to the existing acquisition system.

A Novel Approach to improve Speech Intelligibility through Critical Band Enhancement

In communication systems involving speech, two different environments can be identified. These are categorized as far-end environment and the near-end environment. These different environments lead to different causes for reduction in speech intelligibility for the listener. By applying noise reduction techniques, the impact of acoustical noise sources in the far-end environment can be minimized. However, the effect of the noises present at the near-end environment cannot be negated because the listener perceives the speech and noise simultaneously. Thus near-end listening enhancement approach must be employed to enhance the speech signal to improve the speech intelligibility, when the near-end noise dominates. This work focuses on developing an approach to enhance the speech signal critical band-wise, after analyzing far-end speech and near-end (background) noise energy. Enhancedspeech signal intelligibility is assessed in terms of Speech Intelligibility Index (SII). The results obtained indicate an improvement in speech intelligibility, which can be confirmed through the values of SII.

Design of area and power efficient complex number multiplier

Complex number multiplication is one of the most important arithmetic operations in signal processing. The paper proposes a design of high speed 8-bit complex number multiplier where the multiplication process is carried out using Vedic Mathematics [1], Urdhva Tiryagbhyam (Vertically and Cross-wise) sutra and the addition achieved by use of modified adder architectures to reduce the area occupied and power dissipated. Multiplication is realized using modified 8-bit multipliers [2]. The proposed 8-bit multiplier [2] results in a 6.23% increase in speed, 1.88% decrease in area and 13.84% decrease in power dissipation when compared to the normal 8-bit Vedic multiplier. Further, the proposed 8-bit complex number multiplier results in a 9.11% decrease in power dissipated when compared to the normal 8-bit complex number Vedic multiplier.

Development of LIN 2.1 Driver with SAE Standards for RL78 Microcontroller

Communication Protocols play a vital role in the functioning of various communication systems. LIN is cheaper compared to other communication protocols and is used wherever low costs are essential and speed is not an issue. To enable cold start in case of diesel engines, the cylinders are fitted with glow plugs to preheat the cylinder. The signals for controlling the GLPs are sent using LIN bus from the ECUs. This paper involves design and implementation of LIN 2.1 driver for RL78 microcontroller and configuration of IDs for communication of messages between ECU and the driver. The driver is designed to operate in slave mode with fixed baud rate as per SAE standards and incorporates sleep mode and error handling capability. Embedded C codes are written for various modules and are compiled using IAR Embedded Workbench. The functionality of driver is tested using the CANalyzer tool.

Design and performance analysis of FEC schemes in OFDM communication system

Orthogonal Frequency Division Multiplexing (OFDM) is a method of encoding digital data on multiple carrier frequencies. It has become a prevalent technique for wideband digital communication. Forward Error Correction (FEC) schemes for OFDM communication system is presented in this paper. Interleaver is a vital part in the communication system design. Matrix interleaver implementation which significantly improves the Bit Error Rate (BER) performance over other interleaver designs is proposed. Simulation and analysis of OFDM communication system is carried out with reference to IEEE 802.16 WiMAX standard. Four FEC schemes were developed from the combinations of convolutional encoding and interleaving. The BER performance analysis and comparison of four different FEC schemes are obtained. Among them, the single convolutional coding and dual interleaving performs the best under all ranges of Signal to Noise Ratio (SNR).

Lower and higher critical band enhancement to attain intelligibility improvement in noisy environment

In mobile communication systems, deterioration in intelligibility of the voiced content of the signal is a commonly observed phenomenon. In order to counter the undesirable effect of background noises on the speech signal, a methodology must be developed such that there is no loss in intelligibility of the speech signal. This work focuses on developing an approach to attain enhancement of speech critical band-wise, when the near-end noise dominates. Two different approaches are employed for speech enhancement. First approach involves enhancing the lower critical bands while the second approach includes higher critical band enhancement. The intelligibility is measured in terms of Speech Intelligibility Index (SII). The SII values infer an improvement in speech intelligibility for higher critical band enhancement.

Implementation of operand decomposition in signed logarithmic multipliers

Digital signal processing applications mainly make use of multipliers which determine the overall performance of the system. The existing multiplier architectures are very complex and consume more time. Mitchells Algorithm (MA) is a modest approach to compute the product using simple logarithmic operations and thus, achieving higher speed. Operand Decomposition (OD) reduces the switching activity and hence, achieves a better accuracy in fractional part calculation of logarithm. Divided Approximation (DA) and Table of Correction Values (TCV) are error correction approaches for MA which tries to follow the logarithmic curve more closely. Signed logarithmic multiplication using operand decomposition is proposed. The existing MA, DA and the proposed signed MA-OD, OD-DA, TCV are coded using Verilog HDL, simulated using ModelSim and synthesized using Xilinx XST. The simulated results are compared with respect to mean absolute error. The comparison results show that OD-DA and TCV significantly improve the accuracy of MA and found to decrease the mean absolute error of MA from around 5.36% to 1.7% and 1.33% respectively.

A novel method of wideband acquisition and anti-sideband lock in PM receivers using FFT

A significant problem in a phase locked loop (PLL) is the initial acquisition. High resolution is a major requirement in phase modulation (PM) receivers; however, such accuracy is hindered by side band locking in the existing PM detectors. A Fast Fourier Transform (FFT) based anti-sideband locking scheme is proposed for wide band acquisition in PM receivers. It takes into purview the problems encountered in a narrow loop bandwidth based PLL which restricts the pull-in range and decreases the probability of locking in high frequency offset cases. The proposed design utilizes an in-phase & quadrature-phase (I-Q) detector in order to obtain the frequency offset component and to reduce the sampling frequency. Greater precision in the frequency of the offset signal is achieved with the help of a window based interpolation scheme. PLL operates at a frequency close to the frequency offset and therefore the problem of locking on to the side bands is eliminated completely. The entire PM receiver is realized using MATLAB Simulink. Simulink results confirm fast acquisition, reliable locking and proper demodulation of the PM wave at varying modulation indices.