B. Tillack

SiGe HBT technology with f T /f max of 300GHz/500GHz and 2.0 ps CML gate delay

A SiGe HBT technology featuring fT/fmax/BVCEO=300GHz/500GHz/1.6V and a minimum CML ring oscillator gate delay of 2.0 ps is presented. The speed-improvement compared to our previous SiGe HBT generations originates from lateral device scaling, a reduced thermal budget, and changes of the emitter and base composition, of the salicide resistance as well as of the low-doped collector formation.

Novel collector design for high-speed SiGe:C HBTs

We describe a novel collector design for high-frequency SiGe:C HBTs without deep trenches and with low-resistance collectors formed by high-dose ion implantation after shallow trench formation. f/sub T/ values of 200 GHz at BV/sub CEO/=2.0 V and ring oscillator delays of 4.3 ps are obtained. Excellent static characteristics and high yield were achieved for the HBT module integrated in a 0.25 /spl mu/m CMOS platform.

A flexible, low-cost, high performance SiGe:C BiCMOS process with a one-mask HBT module

We demonstrate an extremely simple, flexible, and hence low-cost SiGe:C BiCMOS process with ample performance for the majority of high volume applications. This technology offers three HBT devices with f/sub T//BV/sub CEO/ values of 28 GHz/67 GHz/7.5 V; 52 GHz/98 GHz/3.8 V; and 75 GHz/ 90 GHz/2.4 V by adding only one mask to the underlying CMOS process.

SiGe:C BiCMOS technology with 3.6 ps gate delay

A high-speed SiGe:C HBT technology is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base-collector capacitance. A ring oscillator delay of 3.6 ps per stage was achieved. To our knowledge, this is the shortest gate delay reported to date for a SiGe technology. The HBTs demonstrate an f/sub T/ of 190 GHz, an f/sub max/ of 243 GHz, and a BV/sub CEO/ of 1.9 V at an drawn emitter size of 0.175/spl times/0.84 /spl mu/m/sup 2/. The high-speed HBT module has been integrated in a 0.25 /spl mu/m CMOS platform.

Dopant diffusion in C-doped Si and SiGe: physical model and experimental verification

We show that B and P exhibit suppressed, and As and Sb enhanced diffusion in C-rich Si. This can be well described by coupled diffusion of C and Si point defects. We present a physical model for the impact of C on dopant diffusion in Si and SiGe and demonstrate its reliability in the context of device characteristics of heterojunction bipolar transistors, which constitute a most sensitive tests for dopant diffusion on the nm scale.

SiGe HBT module with 2.5 ps gate delay

We present a double-polysilicon SiGe:C HBT module showing a CML ring oscillator (RO) gate delay tau of 2.5 ps, and fT/ fmax/BVCEo values of 300 GHz/350 GHz/1.85V. A key new feature of the HBT module is a connection of the extrinsic and intrinsic base regions by lateral epitaxial overgrowth. This facilitates simultaneously a very low base resistance and a reduced base-collector capacitance. In addition, the RF performance is enhanced for devices rotated by 45deg with respect to the standard orientation due to favorable epitaxial growth behavior.

SiGe BiCMOS Technology with 3.0 ps Gate Delay

This work reports on a 130 nm BiCMOS technology with high-speed SiGe:C HBTs featuring a transit frequency of 255 GHz and a maximum oscillation frequency of 315 GHz at an emitter area of 0.17 x 0.53 mum². A minimum gate delay of 3.0 ps was achieved for CML ring oscillators. Breakdown voltages of the HBTs are measured to be BV_CEO=1.8 V, BV_CBO=5.6 V, andBV_EBO=1.9 V.

A Low-Cost, High-Performance, High-Voltage Complementary BiCMOS Process

The authors demonstrate a low-cost, high-performance, high-voltage complementary SiGe:C BiCMOS process. This technology offers three npn SiGe:C devices with f_T/BV_CEO values of 40GHz/5V, 63GHz/3.5V, and 120GHz/2.1V together with a 32GHz f_T/35GHz f _max/ 4.4V pnp SiGe:C HBT by adding only three bipolar masks to the underlying RF-CMOS process. With two additional implant masks, a 150GHz, 2.2V npn HBT and either a 43GHz f_T/ 65GHz f_max 4.2V pnp or a 38GHz f_T/ 70GHz f_max, 5.8V pnp device can be fabricated additionally (in the npn case) or alternatively (pnp case) to the devices of the 3-mask module

HBT before CMOS, a new modular SiGe BiCMOS integration scheme

Demonstrates a novel HBT-before-CMOS integration scheme to integrate SiGe:C HBTs with a 130 nm gate length CMOS frontend. This scheme entirely eliminates the impact of the HBT thermal steps on CMOS characteristics, opening the way for easy, modular integration of high-performance HBTs into highly scaled CMOS technologies. C doping of the SiGe layer prevents the degradation of HBT parameters by critical CMOS thermal steps. This is demonstrated for SiGe:C HBTs with f/sub T//f/sub max/ values of 80/90 GHz fabricated in the HBT-before-CMOS scheme and in a benchmark HBT-only process.

Latchup immunity and well profile design by a deep carbon-doped layer

We show that good latchup immunity and RF characteristics can be achieved by a deeply buried carbon-doped layer on p substrate. The inserted layer stack allows more flexible design of well doping profiles, thus reducing sheet resistances and parasitic capacitances, while maintaining CMOS device performance and design flexibility.