Babak Mohammadi

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-V T memory in 65nm CMOS

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust sub-VT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leakage 4kb SCM manufactured in 65nm CMOS technology. To minimize leakage power during standby, a single custom-designed standard-cell (D-latch with 3-state output buffer) addressing all major leakage contributors of SCMs is seamlessly integrated into the fully automated SCM compilation flow. Silicon measurements of a 4kb SCM indicate a leakage power of 500fW per stored bit (at a data-retention voltage of 220 mV) and a total energy of 14 fJ per accessed bit (at energy-minimum voltage of 500mV), corresponding to the lowest values in 65nm CMOS reported to date.

Dual-V T 4kb sub-V T memories with <1 pW/bit leakage in 65 nm CMOS

Two standard-cell based subthreshold (sub-VT) memories (SCMs) are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual-VT approach to improve reliability and balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implementation; and 2) a purely MUX-based implementation with the first stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65nm CMOS technology show that read access speed increases by 4× and 8× compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7× and 2× to 39 and 29 fJ, respectively.

A 65 nm single stage 28 fJ/cycle 0.12 to 1.2V level-shifter

A conventional level-shifter is modified to extend the operation range down to subthreshold regime. Leakage current is reduced by utilizing transistor stacking, channel stretching, and reverse body biasing. The design has a standard-cell compliant layout and is fully integrated in a conventional digital design flow. The level-shifter is manufactured in 65nm CMOS, and functionality is verified by measurements. The proposed design is capable of converting 0.12 to 1.2V in a single stage, and has a static power consumption of 640pW at a 0.12 to 1V conversion. The minimum energy/cycle of 28 fJ/cycle with a conversion speed of 72MHz was observed at 0.3 to 1V conversion.

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch architecture designs, and process options. Furthermore, deployment of multiple threshold voltages (Vth) options in a single standard-cell/bitcell enables additional architectural choices. Silicon measurements from five memory designs, optimized at the transistor level in conjunction with gate-level optimizations, are considered to demonstrate the different trade-off corners. Measurements show that substituting the storage element in an SCM with a D-latch using transistor stacking and channel length stretching results in lowest leakage power. Alternatively, a pass- transistor based latch as storage element reduces the area footprint at a cost of reduced access speed, which can be compensated by using a lower-Vth pass-transistor. However, relatively high speed (tens of MHz) in the near- to subthreshold (sub-Vth) region is achievable if general purpose transistors are used instead of low power transistors. A discussion is included to illustrate when to implement ULV memories using SCMs and when to choose sub-Vth SRAMs. The discussion shows that the border is between 4-6 kb, depending on the number of words and the wordlength configuration.

A 35 fJ/bit-access sub-V T memory using a dual-bit area-optimized standard-cell in 65 nm CMOS

A 128×32 bit ultra-low power (ULP) memory with one read and one write port is presented. A full-custom standard-cell compliant dual-bit latch with two integrated NAND-gates was designed. The NAND-gate realizes the first stage of a read multiplexer. A dense layout reduces the physical cell area by 56 %, compared to a pure commercial standard-cell equivalent. Effectively, an overall memory area reduction of 32%is achieved. The gates are integrated into a digital standard-cell based memory (SCM) flow. Silicon measurements show correct read and write operation deep in the subthreshold domain (sub-VT), down to 370mV, and data is retained down to 320mV. At the energy minimum voltage (450 mV) the memory dissipates 35 fJ/operation.

A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI

In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240mV and the retention voltage is found at 200mV.

Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS

A low power CMOS charge pump (CP) is proposed utilizing a new combination of charge transferring switches for a faster start-up, higher efficiency and lower reverse charge sharing. A low cost feedback mechanism observes the output voltage level and automatically switches off the clock after passing a threshold, which reduces energy dissipation by 62%. It is shown that by using one capacitor per stage, the proposed architecture reaches higher voltages compared to the competitive architectures when driving capacitive loads. The design is manufactured in a 65 nm technology, and measurement results confirm a 120% higher voltage compared to the conventional Dickson CP at 400 mV with identical area cost. The measured minimum operating voltage and highest charge pumping efficiency are 290 mV and 86%, respectively.

A 0.28¿0.8V 320 fW D-latch for sub-VT memories in 65 nm CMOS

The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power.

A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD–SOI

A 128-kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in 28-nm FD–SOI technology is presented. An ideal power management scenario in a single supply system is achieved by permanently keeping the storage elements in the vicinity of the retention voltage. Performance and reliability is regained by boosting the voltage on critical nodes. The cost of voltage boost generation unit is minimized by 66 low-power and area efficient ON-chip charge pumps, i.e., 64 for boosting the voltages on write-bitlines and two for the wordlines. The charge pump energy overhead is reduced by introducing a new boost paradigm with an on-demand activation mechanism that generates the required boost level in a single clock cycle. A sense amplifier-less read architecture enables a reliable and high performance read operation. Measurements identify several meritorious metrics. The minimum read energy is identified as 8.4fJ/bit-access, achieved for 90-MHz operation at 0.3V. Furthermore, the minimum operating voltage is measured as 240mV, and data is retained in ultra-low voltage regime, ranging down to 0.2V. The bitcell area, implemented using standard design rules, is 0.261

An area efficient single-cycle xV DD sub-V th on-chip boost scheme in 28 nm FD-SOI

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