Balaji Vaidyanathan

Architecting Microprocessor Components in 3D Design Space

Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional (3D) chip architectures, with its intrinsic capability to reduce the wire length, is one of the promising solutions to mitigate the interconnect related issues. In this paper we implement a few components of a microprocessor using custom design to show the potential performance and power benefits achievable through 3D integration under thermal constraints. We also introduce a standard cell based 3D design flow which leverages the commercial 2D design tools. Using this design flow we provide performance results of wide range of arithmetic units in 3D, thus introducing a fast method to analyze the performance benefits of 3D designs. In contrast to prior work, which mostly investigates single components of a processor, our work takes multiple components into consideration and the experimental results are promising in terms of delay and power reductions. Complex designs in 3D that have equivalent performance compared to a simple 2D designs is taken for IPC improvement analysis. An IPC improvement of 11% shown for a microprocessor implemented in 2-strata 3D technology

Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model

Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET models to accurately capture the nonlinear properties of submicron MOS transistors. Based on these models, we propose and validate the transient pulse generation model and propagation model for soft error rate analysis. The pulse generated by our pulse generation model matches well with that of HSPICE simulation, and the pulse propagation model provides nearly one order of magnitude improvement in accuracy over the previous models. Using these two models, we propose an accurate and efficient block-based soft error rate analysis method for combinational logic circuits.

Technology Scaling Effect on the Relative Impact of NBTI and Process Variation on the Reliability of Digital Circuits

The impact of negative bias temperature instability (NBTI) on circuit reliability is typically assessed without accounting for the variability associated with the manufacturing process. With technology progression, manufacturing process variability scales more aggressively than transistor NBTI lifetime. Hence, a clear link between transistor and circuit reliability that takes variability into account is imperative to analyze circuit reliability. We propose a figure of merit termed fall-out to describe the proportion of circuits whose frequencies would exceed the initial manufacturing distribution. We use fall-out to assess NBTI and process variability in tandem, and we show that the fall-out of circuit frequency (or timing delay) peaks and diminishes as technology scales. We propose that the fall-out of a ring oscillator can be used as a worst-case indicator of circuit reliability in any given technology.

NBTI-aware statistical circuit delay assessment

This work establishes an analytical model framework to account for the NBTI aging effect on statistical circuit delay distribution. In this paper, we explain how circuit NBTI mitigation techniques can account for this extra variability and further present the impact of statistical PMOS NBTI DC-lifetime variability on the product delay spread.

Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning

Random process variation and variability intrinsic to PMOS Negative Bias Temperature Instability (NBTI-induced statistical variation) are two major reliability concerns as transistor dimensions scales with technology. Previous works have studied these two sources of variation separately at device and circuit level. We study the impact of the interaction between intrinsic PMOS NBTI variability and time process variability on circuit delay spread. A statistical pipeline timing error model is proposed including both the variability sources to predict its impact on pipeline stage count. It is shown that a wide difference in statistical timing response to intrinsic NBTI variability exists among different circuits. Traditional design time NBTI-aware delay guard-banding is proved to be statistically insufficient in pipelines and an excess of 2x guard-band needs to be incorporated at the end of 10 years. However, the guard-band is shown to be reduced by 30% when the dynamic cycle time stealing technique is employed.

The relationship between transistor-based and circuit-based reliability assessment for digital circuits

Logic, analog, RF, SRAM, and DRAM circuits respond differently to NBTI and HCI induced time dependent parametric shifts. We analyze digital logic susceptibility to these transistor degradation mechanisms and identify the benefits of simulation based aging-induced reliability assurance at the product level.

Soft error rate cross-technology prediction on embedded DRAM

Embedded DRAM has been widely used in System on Chip (SOC) systems due to its higher density than SRAM. Embedded DRAM soft error rate (SER) has become an important subject since more embedded dynamic random access memories (DRAM) are now embedded on the chip as technology advances. Experiments show alpha-SER rapidly declines with embedded DRAM scaling while neutron-SER is less significantly impacted. We develop a simple and rapid method to predict neutron- and alpha-SER scaling trends for embedded DRAM without the use of complicated simulation procedures.

Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors

Chip multiprocessors are becoming increasingly popular in embedded domain since they have important advantages over their single core counterparts from the parallelism, power efficiency, validation, and verification perspectives. However, extracting maximum performance from these multiprocessors requires compiler support in form of effective code parallelization. The goal of this paper is to present and experimentally evaluate a locality aware dynamic loop scheduling strategy that implements both locality aware loop iteration distribution across parallel processors and dynamic load balancing at runtime. This hybrid scheme has been implemented and tested along with four other previously-proposed loop scheduling schemes, including a locality aware one. Our experimental analysis reveals that the proposed approach generates better results than all other scheduling schemes (static or dynamic) tested. Our results also show that the improvements brought by the proposed scheduling scheme are consistent across experiments with different values of our major simulation parameters such as the number of processors and cache size per processor

Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression

Code compression techniques have been proposed to mitigate the problem of limited memory resources in embedded systems. As technology scales, reducing on-chip bus energy consumption is becoming important for embedded system designers. In this paper, we propose a crosstalk-aware energy-efficient code compression scheme, which can reduce inter-wire coupling transition induced instruction bus energy consumption, without sacrificing compression ratio. The experimental results show that the bus power consumption due to inter-wire coupling transition alone is reduced by 42-68% and the total bus power consumption is reduced by 55-71% for TMS320C6x benchmarks.

A Process Scheduler-Based Approach to NoC Power Management

Increasing use of on-chip networks as communication infrastructure in both high performance and low end computing makes it important to consider their power consumption. Several previously proposed approaches to power management in the context of NoCs (network-on-chips) are either pure hardware based or focus exclusively on a single application execution scenario. This paper makes two major contributions. First, it proposes a software-based proactive on-chip network power management scheme that operates under a given process scheduler. Second, it presents a power-aware process scheduling strategy, with the goal of maximizing power savings when we have multiple applications in the system. The paper also evaluates the proposed schemes under the different execution scenarios in the context of NoCs based on a two-dimensional mesh topology and compares them to each other as well as to a previously-proposed hardware-based network power management scheme. Our experimental evaluation using six data-intensive applications shows that the proposed software based approach is competitive with the hardware based scheme. Also, we found that the power aware scheduling brings significant energy savings