Balsha R. Stanisic

Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization

An important and largely unexplored aspect of power distribution synthesis is cell customization. Through automatic cell customization, power I/O cell assignments and local substrate and power supply decoupling may be tailored to reduce deleterious noise effects on analog circuits in mixed-signal environments. Techniques for simultaneous power grid design (topology and sizing) and cell configuration/customization are described that allow designers to handle more difficult chip-level noise problems. Synthesis results on an industrial mixed-signal example demonstrate the effectiveness of this approach. >

Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs

The move to higher levels of integration has increased the fraction of application-specific integrated circuit (ASIC) designs containing both analog and digital circuits. While the die area for the analog portion of these chips is modest, the design time is often significant. This has motivated the development of automated analog physical design tools for cell-level place-and-route and system-level signal-integrity-routing. To date, there is no tool that has specifically addressed the critical design task of synthesizing the power distribution for the analog portion of an analog or mixed-signal ASIC. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs describes algorithms for analog power distribution synthesis and demonstrates their effectiveness. Existing digital power bus synthesis algorithms have failed to address critical concerns for analog circuitry, thus yielding unacceptable results. These tools synthesize only the bus component of power distribution networks and only consider simplified DC aspects of macros and busses. Readers of the companion book in this series, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits (Kluwer Academic Publishers), already recognize the inadequacy of this simplified view of the noise and power distribution problem in mixed-signal integrated circuits. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs addresses power distribution synthesis for mixed-signal integrated circuits. Several key challenges in power distribution design are identified and automated methods to overcome them are described. This book presents a new formulation for the analog power distribution synthesis problem which synthesizes both the power busses power I/O cell assignment by evaluating DC, AC, and transient interaction between the macros, busses, chip substrate, and package. Furthermore, algorithms are introduced which simultaneously optimize power I/O cell assignment, macro cell substrate coupling, power bus topology selection and power bus sizing. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs will be of interest to CAD designers and researchers specializing in physical design, modelling and circuit synthesis.

Mixed-signal noise-decoupling via simultaneous power distribution design and cell customization in RAIL

An important and largely unexplored aspect of power distribution synthesis is cell customization. Through cell customization, power I/O cell assignments and local substrate and power supply decoupling may be tailored to reduce deleterious noise effects on analog circuits in mixed-signal environments. In this paper, we describe techniques for simultaneous power grid design (topology and sizing) and cell configuration/customization which allow designers to handle more difficult chip-level noise problems. We have incorporated this new approach in the power distribution synthesis tool RAIL and demonstrate its effectiveness on an industrial mixed-signal example.<<ETX>>

Modeling of Analog-Digital Loops in VHDL

The previous chapters introduced the engineer to some of the basic concepts in using VHDL for behavioral modeling. This chapter is written to assist the applications engineer familiar with Automatic Gain Control (AGC) and Phase-Locked (PL) loops in applying those concepts. The intention is to incorporate loop behavior into analogdigital modeling and demonstrate the resulting analog-digital simulation. Described is an approach for modeling combined analog-digital loop behavior -- centered on the VHDL behavioral models used to simulate the AGC and PL loops. This approach enables the VHDL simulation of mixed analog-digital hardware designs incorporating these control loops.

Behavior Modeling of Mixed Analog-Digital Circuits

Over the past few years a number of simulation approaches for mixed analog-digital hardware designs have been described. The IEEE standard Hardware Description Language (VHDL), standardized by the IEEE in 1987 and primarily used to model digital behavior, also has the descriptive capability to model analog behavior for event-driven simulation [4]. This chapter describes an approach for mixed analog-digital event-driven simulation and physical design verification using VHDL. Specifically, this chapter presents a general VHDL simulation model and a standard-cell based physical design verification methodology. It demonstrates the applicability of this general simulation model to transfer function modeling through a detailed amplifier example. This general simulation model and its associated physical design verification methodology were used to verify both the analog-digital functional interaction and the physical interconnection of a Bipolar/CMOS chip (5.5mm × 5.5mm) used in hard disk drive products.

DC, AC, and Transient Electrical Models and Analysis

We considered the physical design and optimization formulation for simultaneous power I/O cell assignment, power bus topology, and power bus sizing synthesis in the proceeding chapter, but we have still only addressed part of the problem. In this chapter, we complete our power distribution synthesis formulation by describing the electrical modeling and electrical evaluation strategy used to meet our electrical objectives and constrain DC, AC, and transient behavior. We highlight AC and transient behavior, the major concerns as yet unaddressed to our knowledge in power synthesis. We will describe a method to consider this critical part of design in mixed-signal integrated circuits and also describe improvements in handling DC behavior.

Physical Design and Optimization

In the previous chapter, we pointed out the lack of power distribution synthesis methods and summarized several shortcomings in previous power bus synthesis approaches. This chapter presents a new approach to synthesize power distribution and to alleviate many of these shortcomings. We describe our new optimization-based strategy which consists of physical design, optimization, electrical modeling, and electrical evaluation components. Specifically, this chapter formulates the physical design and optimization aspects of power distribution synthesis, but only incorporates high-level electrical modeling and electrical evaluation into this strategy. We postpone describing in detail the incorporation of all the electrical aspects until the next chapter. We begin by extending the work previously described in the macro-2D custom design style, and focus on creating new synthesis strategies to handle analog power distribution concerns. We discuss our design style selection and illustrate its generality. We discuss our design objectives and new formulations for power bus topology selection and sizing. We describe the algorithms to synthesize the power I/O cell assignment and power bus topology and sizing, all simultaneously. Next, we formulate the simultaneous power bus synthesis and power I/O cell assignment problem and describe why we chose simulated annealing optimization. We review simulated annealing and then describe our specific annealing formulation for the power distribution synthesis problem.

Power Distribution Noise and Physical Design Methods

In the previous chapter, we introduced our work and in this chapter, we continue by laying the foundation for our research. There are several design aspects affecting power distribution and we begin by describing the design problem traits characteristic of the analog portion of analog or mixed-signal ASICs. Then, we discuss and illustrate the commonly used physical design styles in these ASICs. Next, we describe key design concerns associated with analog power distribution and highlight previous synthesis methods used to automate part of this design task. We complete this chapter by evaluating how well the previous synthesis methods support design styles and address the critical physical design and electrical issues.

Modeling of Transmission Line Effects in Digital Circuits

This chapter is written to assist the applications engineer familiar with transmission line behavior in improving digital simulation by incorporating transmission line behavior into digital models. It describes an approach for simulating the combined digital logic-transmission line behavior and centers on the VHDL behav’oral models used to simulate transmission line effects that enable simuIation of of chip environments such as multichip modules and cards.