Barry Syrett

Correlation of Scattering Loss, Sidewall Roughness and Waveguide Width in Silicon-on-Insulator (SOI) Ridge Waveguides

We use star couplers to measure the relative scattering losses of silicon-on-insulator (SOI) ridge waveguides of various widths over the range of 1.75 to 0.2 mum in a single measurement. The scattering loss data obtained for waveguides fabricated by different photolithography and e-beam base processes correlate well with the measured root-mean-square roughness of the waveguide sidewalls obtained using SEM image analysis, and are in qualitative agreement with the prediction of simple scattering loss theory.

Modeling of current lag in GaAs IC's

Leakage currents, thermal effects and deep-level traps cause significant current lag effects in GaAs MESFETs. A conventional, MESFET large-signal, equivalent-circuit model has been modified to simulate these effects and used to improve the design of GaAs digital control and RF switching circuits. Both gate lag and drain lag are simulated as well as over-shoot or under-shoot behavior.

Modeling the drain current of the dual-gate GaAs MESFET

A new empirical model of the dual-gate GaAs MESFET (DGFET) drain current is presented. The model uses a modified expression of the well-established hyperbolic tangent-function to accurately fit the DC and the RF I/V characteristics of the DGFET. The frequency dispersion of the DGFET transconductances and output conductance is taken into account in the new model. The new model is tested on many devices of different topologies. Very good agreement between the measured and the calculated I/V characteristics over a wide range of bias conditions is achieved.

SOI Waveguide Fabrication Process Development Using Star Coupler Scattering Loss Measurements

We show that integrated optical star couplers can be useful characterization devices to measure the sidewall roughness-induced scattering losses of planar waveguides. We describe the detailed fabrication processes of these star couplers on the silicon-on-insulator (SOI) platform and the process improvements implemented to reduce the waveguide sidewall roughness and scattering loss. We report the main process challenges, particularly to assure a clear gap between any adjacent waveguides of the dense and closely spaced output waveguide array. These challenges are addressed by optimizing the exposure dose of the resist and adding an oxygen ashing treatment to eliminate waveguide footings. We demonstrate further improvement on the waveguide profile and sidewall roughness through the use of a thin Cr hardmask for the dry plasma etching. This optimized fabrication process is capable of producing approximately a 3 nm root-mean-square sidewall roughness, measured using both scanning electron microscopy (SEM) and atomic force microscopy (AFM). Using the fabricated star couplers, we manage to measure the relative scattering losses of various waveguides with the width varying from 0.2 to 2.0 μm in a single measurement, and show that the measured losses agree with the measured sidewall roughness.

Power and speed analysis of miniaturized SOI y-branch Mach-Zehnder thermo-optic switches

We calculate the π-power and rise time for several 1×1 y-branch MZI SOI thermo-optic switches as a function of device size. These switches consist of waveguide core thickness ranging from 10 to 0.22 μm. Upon scaling the core thickness, the best power and speed performance occurs at 0.7 μm. Further miniaturization results in an increased power and reduced speed, mainly due to the mode expansion from the core into the cladding. We show that varying the MZI arm separation is an effective approach to improve the performance of miniaturized thermo-optic switches.

Modeling substrate integrated waveguide structures using effective material properties

A substrate integrated waveguide is analyzed using effective material properties for the first time. The analysis is performed by replacing subwavelength periodic metallization with a frequency dependent homogeneous material. For example, the post wall of the waveguide is represented as a negative permittivity material. A substrate integrated waveguide fabricated in low temperature co-fired ceramic is analyzed. The phase constant of the guide is calculated with slab waveguide equations, using effective material properties to replace much of the metal structuring, and it is shown to be almost the same as that simulated and measured. An SIW coupler that utilizes side wall leakage for coupling is simulated using effective material properties. The simplified structure shows results matching the full structure with a reduction in simulation time of 88%. These results demonstrate a substrate integrated waveguide can be accurately and efficiently simulated by replacing subwavelength periodic structures with a frequency dependent homogeneous material.

A low cost oscillator for high data rate E-band transceivers

This paper proposes an oscillator design capable of achieving high data transmission rates of up to 1.5 Gbps with a modulation scheme of 256 QAM at E-band frequencies. A low phase noise oscillator and high quality factor resonator are implemented in this work. The proposed cavity resonator design is embedded in a low cost gold plated brass casing. Eigenmode simulations yield an unloaded quality factor in excess of 5800 at 20 GHz. The low phase noise oscillator comprises of commercially available and low cost components surface mounted on a low loss millimeter-wave substrate. The proposed 20 GHz oscillator makes use of a frequency doubler to drive a sub-harmonically pumped mixer aimed for E-band frequencies of 80 GHz. The expected phase noise of the oscillator is better than −103 dbc/Hz with 100 kHz offset while operating at 80 GHz.

Performance Optimization of a Reconfigurable Waveguide Digital Optical Switch on InGaAsP/InP

The performance of a compact 1times2 switch actuated by carrier injection is improved through optimization of design and operating parameters. Devices exhibit better than 25 dB contrast ratio for less than 20 mW driving power

Low-current optical switching by carrier-injection-induced reconfigurable waveguiding

An improved compact 1x2 digital optical switch (DOS) in InGaAsP/InP is studied, and the experimental results are compared to numerical modeling. We present measurements of Mach-Zehnder and DOS devices fabricated with InGaAsP cores having bandgap energies corresponding to wavelengths of 1.2 um, 1.3 um, and 1.4 um. The results are compared with modeling evaluation of refractive index change versus carrier concentration in the different InGaAsP alloys. The effects of modifications in the wafer layer structure are presented as well. Switching current is significantly reduced from greater than 100 mA to about 20 mA, resulting in significant power savings, and in addition eliminating thermal overshoot in the switched optical pulse. The DOS has a measured switching contrast ratio of better than 12 dB with a switching rise time of less than 10 nsec.

InGaAsP digital optical wwitch on InP

We demonstrate Digital Optical Switches (DOS) on InP based on carrier-injection and on the quantum-confined Stark effect (QCSE). The active waveguide core is composed of either a double-heterostructure of InGaAsP for carrier-injection or a InGaAs-InGaAsP for reverse bias operation. O-Ion implantation was employed to isolate the branches of the DOS instead of the usual isolation by etching employed elsewhere.