Bartek Pawlak

Solid phase epitaxy versus random nucleation and growth in sub-20nm wide fin field-effect transistors

The authors investigate the implications of amorphizing ion implants on the crystalline integrity of sub-20nm wide fin field-effect transistors (FinFETs). Recrystallization of thin body silicon is not as straightforward as that of bulk silicon because the regrowth direction may be parallel to the silicon surface rather than terminating at it. In sub-20nm wide FinFETs surface proximity suppresses crystal regrowth and promotes the formation of twin boundary defects in the implanted regions. In the case of a 50nm amorphization depth, random nucleation and growth leads to polycrystalline silicon formation in the top ∼25nm of the fin, despite being only ∼25nm from the crystalline silicon seed.

Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193 nm immersion lithography and conventional dry etch. FinFETs with fin widths down to 5nm are achieved with record aspect ratios of 13. Excellent nMOS and pMOS performance is demonstrated for narrow fins and short gates. Further improvement in nMOS performance can be achieved by eliminating access resistance that is currently attributed to poor re-crystallization of implantation damage in narrow fins. Fully-depleted FinFETs show strongly improved short channel effect (SCE) control when the fin width is scaled, even without halo-implants. Nearly ideal DIBL and sub-threshold slope (SS) are achieved down to 30nm gate length. Low leakage devices are realized by combining a fully depleted channel, HfSiO high-k dielectric, mid-gap TiN metal electrodes, and aggressive fin width scaling. Symmetrical threshold voltages (±0.35 V) are achieved. It is demonstrated that selective epitaxial growth on source and drain regions is essential to limit parasitic resistance in narrow fin devices. Parametric spread is dominated by gate length variations in short devices but within-die fin width variations are still evident for long devices.

Multi-gate devices for the 32nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

Doping of sub-50nm SOI layers

Doping of thin body Si becomes very essential topic due to increasing interest of forming source/drain regions in fully depleted planar silicon-on-isolator (SOI) devices or vertical Fin field-effect-transistors (FinFETs). To diminish the role of the short-channel-effect (SCE) control, the Si layers thicknesses target the 10 nm range. In this paper many aspects of thin Si body doping are discussed: dopant retention, implantation-related amorphization, thin body recrystn., sheet resistance (Rs) and carrier mobility in cryst. or amorphized material, impact of the annealing ambient on Rs for various SOI thicknesses. The complexity of 3D geometry for vertical Fin and the vicinity of the extended surface have an impact on doping strategies that are significantly different than for planar bulk devices.

Ultra-Shallow Junctions Formed by Co-Implantation and Sub-Melt Laser Annealing

This paper presents the benefits of both co-implantation of diffusion-retarding species and ultra-fast annealing techniques as studied on blanket and device wafers. F and C co-implantation with B+ for PMOS and P+ for NMOS combined with conventional spike annealing produce reduced junction depths and improved dopant activation and profile abruptness, as measured on blanket wafers and compared to similar implants without the co-implanted species. Device wafers show that the overlap capacitance is reduced, consistent with the shallower junction depths and reduced lateral diffusion. The improved dopant activation manifests itself in reduced series resistance and improved Ion values. Depending on the implant conditions, either the gate/extension overlap capacitance or the series resistance can be improved when sub-melt laser annealing is used instead of conventional spike anneal. For both approaches, scanning spreading resistance microscopy (SSRM) measurements confirm the shallow junction depths and reduced lateral diffusion.