Basab Datta

Low-power and robust on-chip thermal sensing using differential ring oscillators

The increasing significance of thermal issues in modern VLSI motivates the need for a large number of lightweight, robust and power efficient thermal sensors for accurate thermal mapping and management. We propose use of differential ring oscillators (DRO) for thermal sensing, utilizing the temperature dependence of the oscillation frequency. In current starved inverter topology using the 45 nm technology node, they have a resolution of 2degC and a low active power consumption of less than 25 muW which can be reduced further by 60-80% by gating the design. A high threshold design proves to be better in terms of leakage, non-linearity error, overall power consumption as well as sensitivity to power supply variations. The standard deviation in measurement (%) caused by process variations and supply noise is within 3% for low Vt design; it increases to 5% for a high Vt design. In a reduced supply bounce configuration, the measurement error caused due to supply noise can be reduced by 15-60%.

Calibration of on-chip thermal sensors using process monitoring circuits

Remarkable increase in peak power-density values coupled with the hotspot migration caused by workload variance motivates the need for multiple thermal monitoring circuits distributed across the die. The effect of intra-die process-variations on deep sub-micron circuits is significant enough to undermine their robustness. Accordingly, there is change in the response of thermal sensors occupying different process-corners which causes a shift in their calibration-constants. To save on tester cost, modern microprocessors employ a single, 2-point hard calibration model (slope-intercept form). In a multi-sensor environment, a single calibration equation will be rendered ineffective due to sparse sensor distribution that will be afflicted by varying degrees of process-variation. Thus, our aim is to estimate the process-induced drift in the calibration-constants of the thermal sensors. To this end, we propose a novel, supply and temperature independent, process-sensor which offers a high sensitivity of 3.35%/5mV variation in Vth and a low power consumption of 4–25nW. The process-estimates obtained are plugged into an analytical model used to describe the process-dependence of a ring-oscillator based thermal sensor and generate the process-shifted calibration constants. HSPICE simulations in 45nm indicate that in the presence of process-variations having 3-σ variability of +/−15% in all process-parameters, the average measurement error of a ring-oscillator-based thermal sensor with process-corrected calibration constants is reduced by ≫3X for slope and ≫10X for intercept as compared to one with static constants.

Temperature effects on energy optimization in sub-threshold circuit design

Sub-threshold circuits have emerged as a strong candidate for use in future energy-constrained applications. In a non-homogeneous design paradigm containing both sub-threshold and high power-density super-threshold blocks, it becomes imperative to examine the thermal effects on sub-threshold operation. In this paper, we investigate the thermal impact on sub-threshold current, delay and energy and develop analytical models of the same. Unlike super-threshold, the sub-threshold ION increases exponentially with temperature while the ION-to-IOFF ratio degrades by 0.52%°C. While delay decreases, energy increases with temperature due to relative increase in leakage power at the higher temperatures. Studies performed on noise-margins, current/delay variability and sub-Vth interconnects suggest that sub-Vth circuits can retain {power, delay, energy} optimality over a relatively high temperature range of 25¿75°C.

Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors

High die temperatures adversely impact CMOS device operation degrading both performance and reliability of integrated circuits. Dynamic thermal management (DTM) schemes rely on physical sensors to provide them with feedback to ensure an accurate and closed-loop throttling mechanism. Power-density trends in current-generation, high-performance processors motivate the need for multiple, low-power and highly accurate thermal monitoring circuits. Studies performed on power-thermal-characteristics of current processors suggest that better sensor-measurement accuracy translates into power-savings and better system-performance. To this end, we propose a novel, track and hold-based on-chip thermal sensor which provides an accuracy of <1ºC and has a low-power consumption of <25 W. Our design operates using the nominal VDD while at the same time takes advantage of the vastly-increased thermal sensitivity in sub-threshold mode. We also propose two schemes to improve the tolerance of thermal sensors to process-induced variations. The 1st scheme makes use of a leakage-current-sensor to identify the process-corner, selects the appropriate corresponding calibration-table and reduces the sensor-measurement error by 45-70%. The 2nd scheme provides a statistical approach towards mitigating the non-idealities by averaging response from multiple sensor-copies and reduces the measurement error by 65-85%.

Thermal-aware voltage droop compensation for multi-core architectures

As the rated performance of microprocessors increases, voltage droop emergencies become a significant problem. In this paper, two new techniques to combat voltage droop emergencies are explored. First, a direct connection between temperature and processor clock frequency modulation during voltage droops is established. In general, a higher temperature leads to a lower voltage droop with the same processor activity. Thus, processor frequencies can be reduced less at high temperature in an effort to prevent voltage emergencies. Through experimentation, the benefits of temperature-flexible frequency scaling are explored. Second, processor signatures consisting of performance statistics are used to identify when voltage droop compensation is needed in a multicore environment. The use of an independent on-chip interconnect network allows for the sharing of signatures across cores at run time. Signature sharing in combination with frequency throttling is shown to provide an improvement in average run-time performance in a number of cases for an eight-core multiprocessor.

Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance

Repeated interconnects remain the design choice for high-performance global communication due to their clearly defined performance metrics and smooth amalgamation to the VLSI CAD flow. Simultaneous variability in process-voltage-temperature (PVT) causes interconnect performance to fluctuate from its nominal value and hence its an essential analysis needed to decide on timing margins for global wires. Negative Bias Temperature Instability (NBTI) has emerged as the most compelling device reliability concern in deep sub-micron technologies. In this paper, we thoroughly investigate the effects on NBTI-stress on PVT-induced variability in repeated global interconnect performance. The delay-spread due to PVT can deviate by 5-12% in the presence of NBTI stress. We propose 2 schemes to mitigate NBTI-stress effects on interconnect-delay and re-align the delay-distribution with its nominal state. The 1st involves upsizing all repeaters uniformly. A 5% size increment is found to be sufficient to counter the worst-case realistic deviation in delay-spread. The 2nd is a dynamic solution which involves using an NBTI detector circuit to monitor signal activity and assess device-status over a portion of the wire and increasing the drive strength of tunable buffers in the event of NBTI-stress.

Low power on-chip thermal sensors based on wires

Current thermal scaling trends in multilevel low-k interconnect structures suggest an increasing heat density as we move from substrate to higher metal levels. Thus, the deterioration of interconnect performance at extreme temperatures has the capability to offset the degradation in device performance when operating at higher-than-normal temperatures. Existing thermal sensing approaches rely heavily on devices (MOS/diodes). They are optimized for a low area and power overhead but continue to suffer from leakage and self-heating and also, tend to disregard the thermal impact on interconnects. We propose an alternate approach of using interconnects to perform the thermal sensing. With feature-size shrinking, metal layers are closer to the substrate suggesting a strong correlation between interconnect temperature and thermal profile of the underlying substrate. Thus, in addition to quantifying the temperature impact on interconnect signal delay; output of proposed sensors can be used to estimate substrate thermal status as well. The simplistic schemes proposed allow reuse of existing on-chip resources such as drivers and time-digitizers, have a low power requirement and are robust against variations in wire dimensions, non-uniform temperature distribution and supply noise.

A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics

Thermal sensing is a pressing need in stacked 3-D chips with limited number of vertical heat conduits. In 3-D systems with active temperature control, the controller is reliant on sensors placed on individual planes to provide the necessary thermal feedback. To this end we propose a delay-line based thermal-sensor which provides a high temperature-sensitivity, high level of process-robustness and is amenable to the TSV-based communication paradigm used in 3D systems. The temperature-sensitive piece mitigates the high process-susceptibility of 3-D circuits through usage of multiple logic-stages composed of long-channel devices and elimination of common-mode noise on the delay-line pair. The thermal information is conveyed to the controller in the form of a signal-frequency and hence is insensitive to path-mismatch in TSV wires. A high post-digitization temperature sensitivity of 0.82%/°C was achieved. The 1-σ accuracy loss due to process-variations and supply-noise was limited to 0.78°C and 1.06°C respectively indicating a high level of process-tolerance.

Circuit-level NBTI macro-models for collaborative reliability monitoring

The increasing significance of Negative Bias Temperature Instability (NBTI) induced device-reliability degradation presents a compelling reason to perform efficient circuit-level reliability tracking. We propose a novel collaborative monitoring frame-work to track circuit level performance degradation caused specifically by NBTI. We use heterogeneous on-chip sensors to measure environmental and stress parameters and a macro-model to map the device-level degradation information into circuit-level reliability estimates. The macro-model is built using curve-fitted data and provides a practical upper bound of the path-delay-degradation to expect under a given set of dynamic parameters which includes operating conditions, process and stress parameters. Through usage of on-chip sensing resources we minimize the need for extensive circuit-specific analyses and also, the pessimism caused by assuming worst-case operating corners. We validate our approach on ISCAS-85 benchmarks and observe excellent correlation (>0.99) between worst-case SPICE observed and model-predicted path-delay degradation.

Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators

High die temperatures adversely impact CMOS circuit operation degrading performance and reliability of both devices and interconnect. Current thermal scaling trends in multilevel low-k interconnect structures suggest an increasing heat density for the metal layers as a result of which the temperature dependence of logic is matched or often exceeded by that of interconnect. This motivates the need to perform 3-D thermal sensing in deep nanometer designs. We propose a novel sensor design that alleviates the complexities associated with time-to-digital conversion in wire-based thermal sensing. The sensing circuit makes use of wire-segments between individual stages of a ring-oscillator to perform thermal sensing using the oscillator frequency value as the mapping to corresponding wire temperature. Alternatively, the sensor can be tuned to strengthen the thermal sensitivity of the devices over that of interconnects to perform substrate-based sensing. We propose a collaborative scheme to sample the thermal status of the different metal levels and the substrate. The proposed sensor provides a resolution of 1°C while consuming an active power of 65-112µW and its sensitivity to process and supply noise can be minimized through design optimizations.