Bassam Jamil Mohd

QoS-Aware Health Monitoring System Using Cloud-Based WBANs

Wireless Body Area Networks (WBANs) are amongst the best options for remote health monitoring. However, as standalone systems WBANs have many limitations due to the large amount of processed data, mobility of monitored users, and the network coverage area. Integrating WBANs with cloud computing provides effective solutions to these problems and promotes the performance of WBANs based systems. Accordingly, in this paper we propose a cloud-based real-time remote health monitoring system for tracking the health status of non-hospitalized patients while practicing their daily activities. Compared with existing cloud-based WBAN frameworks, we divide the cloud into local one, that includes the monitored users and local medical staff, and a global one that includes the outer world. The performance of the proposed framework is optimized by reducing congestion, interference, and data delivery delay while supporting users’ mobility. Several novel techniques and algorithms are proposed to accomplish our objective. First, the concept of data classification and aggregation is utilized to avoid clogging the network with unnecessary data traffic. Second, a dynamic channel assignment policy is developed to distribute the WBANs associated with the users on the available frequency channels to manage interference. Third, a delay-aware routing metric is proposed to be used by the local cloud in its multi-hop communication to speed up the reporting process of the health-related data. Fourth, the delay-aware metric is further utilized by the association protocols used by the WBANs to connect with the local cloud. Finally, the system with all the proposed techniques and algorithms is evaluated using extensive ns-2 simulations. The simulation results show superior performance of the proposed architecture in optimizing the end-to-end delay, handling the increased interference levels, maximizing the network capacity, and tracking user’s mobility.

Secure Authentication for Remote Patient Monitoring with Wireless Medical Sensor Networks

There is broad consensus that remote health monitoring will benefit all stakeholders in the healthcare system and that it has the potential to save billions of dollars. Among the major concerns that are preventing the patients from widely adopting this technology are data privacy and security. Wireless Medical Sensor Networks (MSNs) are the building blocks for remote health monitoring systems. This paper helps to identify the most challenging security issues in the existing authentication protocols for remote patient monitoring and presents a lightweight public-key-based authentication protocol for MSNs. In MSNs, the nodes are classified into sensors that report measurements about the human body and actuators that receive commands from the medical staff and perform actions. Authenticating these commands is a critical security issue, as any alteration may lead to serious consequences. The proposed protocol is based on the Rabin authentication algorithm, which is modified in this paper to improve its signature signing process, making it suitable for delay-sensitive MSN applications. To prove the efficiency of the Rabin algorithm, we implemented the algorithm with different hardware settings using Tmote Sky motes and also programmed the algorithm on an FPGA to evaluate its design and performance. Furthermore, the proposed protocol is implemented and tested using the MIRACL (Multiprecision Integer and Rational Arithmetic C/C++) library. The results show that secure, direct, instant and authenticated commands can be delivered from the medical staff to the MSN nodes.

FPGA hardware of the LSB steganography method

Steganography is one of the most powerful techniques to conceal the existence of hidden secret data inside a cover object. Images are the most popular cover objects for steganography, and thus the importance of image steganography. Embedding secret information inside images requires intensive computations, and therefore, designing steganography in hardware speeds up steganography. This work presents a hardware design of Least Significant Bit (LSB) steganography technique in a cyclone II FPGA of the Altera family. The design utilizes the Nios embedded processor as well as specialized logic to perform the steganography steps. The design balances the tradeoffs such as imperceptibility, quality and capacity.

An energy-efficient and security aware route selection protocol for wireless sensor networks

In wireless sensor networks WSNs, sensor devices have limited supply of energy. The sensor death due to dissipating battery energy is one of the fundamental design issues in WSNs. Hence, energy efficiency is argued to be the most important requirement for any protocol designed for WSNs. With sensors acting as routers to transport the packets from a source to a destination sensor, multipath protocols are used to discover multiple paths with the objective to improve the reliability, efficiency, and security in WSNs. Selecting the path that minimizes the rate of sensors death and extends the lifetime of the network is the main challenge for multipath protocols. In this paper, we propose a new energy and security aware route selection ESARS protocol for WSNs. The first part of ESARS selects a route that maximizes the network lifetime based on a novel metric. The second part of ESARS finds the optimal security level for the selected path based on the estimated security risk of the path. Traditionally, these two parts are addressed separately in the literature, and this paper combines the two parts in one protocol. The proposed protocol is evaluated and compared with other protocols using both analytical analysis and extensive simulations. The results show that the proposed protocol not only achieves its main objective to extend the network lifetime by significantly reducing the sensors death rate but also uses the most optimal security level for the selected route. Moreover, in ESARS protocol, several threshold parameters were employed to provide flexibility per the needs of the application in which the sensors are used. Copyright

Low power Wallace multiplier design based on wide counters

Multiplication is one of the most basic arithmetic operations. It is used in digital applications, central processing units, and digital signal processors. In most systems, the multiplier lies within the critical path and hence, due to probability and reliability issues, the power consumption of the multiplier has become very important. Moreover, as chips shrink and their power densities increase, power is becoming a major concern for chip designers. The ever increasing demand for portable applications with their limited battery lifetime indicates that power considerations should be a center stone in todays designs and the futures designs. Thus, all this has motivated us to provide a novel circuit design technique for a low power multiplier without compromising the multipliers speed. This paper presents a new power aware multiplier design based on Wallace tree structure. A new algorithm is proposed using high-order counters to meet the power constraints imposed by mobility and shrinking technology. Commonly used multipliers of widths 8, 16, and 32 bits are designed based on the proposed algorithm. The new approach has succeeded in reducing the total number of gates used in the multiplier tree. Simulations on Alteras Quartus-II FPGA simulator showed that the design achieves an average of 18.6% power reduction compared to the original Wallace tree. The design performs even better as the multipliers size increases, achieving a 5% gate count reduction, a 26.5% power reduction, and a 23.9% better power-delay product in 32-bit multipliers. Copyright

ANALYSIS AND MODELING OF FPGA IMPLEMENTATIONS OF SPATIAL STEGANOGRAPHY METHODS

Steganography has become an important method for concealed communication especially through image files. Recent proposed steganographic methods employ multiple levels of complex techniques. Hence, there is an increasing significance for hardware implementation and its performance metrics. The objective of this article is to analyze and model the performance of FPGA hardware implementations of several spatial steganography methods, including: least significant bit (LSB), random LSB, mix-bit LSB and texture method. This paper presents innovative models to estimate energy-to-embed-secret-bit, peak signal-to-noise-ratio (PSNR) energy cost, power and resources in complex systems. Examining the performance results of the FPGA implementations shows that embedding misalignment degrades the performance, and random embedding increases resources by 43% and power by 13%. Furthermore, the mix-bit method has the best results in terms of balancing the energy consumption and PSNR. Moreover, the accuracy of the model to predict the energy to embed a single secret bit is 2%, and the accuracy of the model to predict complex system performance is 1% for hardware resources and 16.6% for power.

Optimization and modeling of FPGA implementation of the Katan Cipher

Lightweight ciphers (e.g., Katan) are crucial for secure communication for resource-constrained devices. The Katan cipher algorithm was proposed for low-resource devices. This paper examines implementing Katan Cipher on field programmable gate array (FPGA) platform. The paper discusses several implementations, with 80-bits key size and 64-bits block size. The energy and power dissipations are examined to select the optimum design. Models for resources and power are derived with average error of 12% and 17%.

Wavelet-transform steganography: algorithm and hardware implementation

Steganography is a powerful method to conceal the existence of secret data inside a cover object. The concealment steps are performed in the spatial domain and/or the transform domain such as wavelet transform. While it is harder to detect, the transform domain steganography involves complex computations. Hence implementing steganography in hardware improves the steganography system performance. The preservation of the entire secret information is one of the main challenges for the transform domain steganography. Errors, introduced by quantisation steps, destroy some of the embedded secret bits. In this paper, we present a novel algorithm to embed and extract the entire secret data in the Haar wavelet-based transform without any secret information loss. This is accomplished by special clipping mechanism as well as modifying the placement of the secret bit in the transform coefficients. The algorithm is implemented in an FPGA-based hardware, and its performance metrics are examined including resources utilisation, power, timing and energy.

Modeling and optimization of the lightweight HIGHT block cipher design with FPGA implementation

The growth of low-resource devices has increased rapidly in recent years. Communication in such devices presents two challenges: security and resource limitation. Lightweight ciphers, such as HIGHT cipher, are encryption algorithms targeted for low resource systems. Designing lightweight ciphers in reconfigurable platform e.g., field-programmable gate array provides speedup as well as flexibility. The HIGHT cipher consists of simple operations and provides adequate security level. The objective of this research work is to design, optimize, and model FPGA implementation of the HIGHT cipher. Several optimized designs are presented to minimize the required hardware resources and energy including the scalar and pipeline ones. Our analysis shows that the scalar designs have smaller area and power dissipation, whereas the pipeline designs have higher throughput and lower energy. Because of the fact that obtaining the best performance out of any implemented design mainly requires balancing the design area and energy, our experimental results demonstrate that it is possible to obtain such optimal performance using the pipeline design with two and four rounds per stage as well as with the scalar design with one and eight rounds. Comparing the best implementations of pipeline and scalar designs, the scalar design requires 18% less resources and 10% less power, while the pipeline design has 18 times higher throughput and 60% less energy consumption. Copyright

A comparative study of steganography designs based on multiple FPGA platforms

Steganography methods conceal covert messages inside communicated data. Field-programmable gate array FPGA hardware implementation provides speed, flexibility and configurability. It is extremely difficult to compare published results from different platforms and technologies. The goal of our research work is to mitigate the dependency by examining implementations from multiple FPGA platforms. The research studies the implementations of 12 spatial steganography methods using Altera and Xilinx FPGAs. The methods include mix-bit LSB, least significant bit LSB, random LSB and texture-based algorithms. The objective of the research is to develop platform-independent resources, timing, power and energy models; to empower future steganography research. Further, the article evaluates steganography methods using typical performance metrics as well as a novel performance metric. The results suggest that the mix-bit methods exhibit good performance across most of the metrics. However, when image quality is a concern, the two-bit LSB is the front runner.