Bassel Soudan

VLSI design exchange with intellectual property protection in FPGA environment using both secret and public-key cryptography

With the advent of multi-million gate chips, field programmable gate arrays (FPGAs) have achieved high usability for design verification, exchange, test and even production. Adding to this is the possibility of reusing readily available licensed IP to shorten the design cycle. A major concern for IP owners is the possible over-deployment of the IP into more devices than originally licensed. In this paper, we propose a system based on both public-key and secret-key cryptography embedded in a secured design exchange protocol for protecting the rights of the IP owner. The system consists of hardware-supported design encryption and secured device authentication protocols. Design encryption based on secured device identification ensures that the IP can only be deployed into explicitly identified and agreed upon devices. The system uses a combination of secret and public-key cryptographic functions devised for an uncomplicated trustable design exchange scenario. The public-key functions use modular squaring (Rabin lock) on the FPGA chip instead of exponentiation to reduce the hardware complexity.

An Evolutionary Dynamic Population Size PSO Implementation

Particle Swarm Optimization (PSO) is a heuristic search method for the exploration of solution spaces of complex optimization problems. The heuristic suffers from relatively long execution times as the update step needs to be repeated many thousands of iterations to converge the swarm on the global optimum. In this work, we explore two dynamic population size improvements for classical PSO with the aim of reducing execution time. Expanding Population PSO (EP-PSO) starts with a small number of particles and iteratively increases the swarm size. Diminishing Population PSO (DP-PSO) starts with a large number of particles and iteratively reduces the swarm size. Simulation results show that both improvements produce almost 60% reduction in the execution time as compared to the classical PSO. However, the results show that EP-PSO fares quite badly when the ability to converge to the global optimum is concerned. DP-PSO performs reasonably compared to the classical PSO but at much faster convergence and execution speeds. Clearly, DP-PSO shows a lot of promise as an enhancement for the classical PSO.

Bio-Inspired Electronic-Mutation with genetic properties for Secured Identification

One essential security weakness in many modern systems is the difficulty of managing secured and provable-identities for all participating entities. In this work we introduce a process for generating a secret provable identity for electronic devices. The identity is created through a random process that is triggered as an electronic-Mutation (EM) once at a user-defined time after device manufacture. The result should be a provable, certified, secret, unclonable, and unchangeable identity that can serve as an electronic DNA (e-DNA) for the device. The identity is self- created similar to naturally occurring Physical Unclonable Functions (PUF), such that it is infeasible even for the unit manufacturer to create duplicate identities. The proposed identity should in difference to PUF evolve through the lifetime of the device allowing for easier detection of fraud attacks. The identity should also possibly diffuse in all system entities similar to the diffusion of biological DNA in all entities of a living organism. Many legal and criminal issues plaguing mass public-commerce, e-Government and mobile systems could be easily resolved through such an identification technology.

Novel secret-key IPR protection in FPGA environment

Some VLSI IP owners prefer to leave programming their IP into a field programmable gate array (FPGA) to the end customer. A major concern is the possible over-deployment of the IP into more devices than originally licensed. In this paper, the authors proposed a system based on secured handshaking with encrypted device and design authentication information ensuring that the IP can only be deployed into agreed upon devices. The system consists of hardware-supported design encryption and secured authentication protocols.

Reducing mutual inductance of wide signal busses through swizzling

On-chip inductive coupling has been shown to depend on the distance wires ran in parallel. It has also been shown to depend on the distance separating an attacker and the victim. This has major effect on global signal busses in high performance microprocessors as they are usually routed as a bundle containing a large number of signals traveling for long distances. A solution has been proposed through a process known as swizzling, where the order of signal wires in the bus is continuously rearranged to move attackers and victims away from each other. This technique has the advantage of reducing the mutual inductance between neighboring wires with zero area or routing resource cost. In this paper, we show a formulation of the swizzling technique and report on some simulation results to highlight the resulting improvements.

Deploying FPGA self-configurable cell structure for micro crypto-functions

This paper discusses the use of features of modern FPGA designs to enable the implementation of highly secure micro crypto-functions. The paper shows a scenario to integrate a dynamic/evolving cipher function in a reconfigurable FPGA architecture. The proposed system offers a practical methodology for building such functions efficiently in modern reconfigurable FPGAs. The resulting cipher, which is secret but still operational and self-evolving, appears to be quite promising for many modern security applications requiring high security, stability and robustness.

Design and implementation of an FTIR camera-based multi-touch display

The personal computer is quickly becoming the center of an all-encompassing multimedia environment. An environment that spans information creation and exchange, entertainment, and near real-life experiential environment manipulation. With such a deluge of media experiences, a new Human-Computer Interface is needed to allow the user better direct manipulation of presented information. In this paper, we present the design and implementation of a camera-based direct interaction multi-touch display. This display replaces the limited interaction afforded by the outdated display monitor and mouse with interactive hands-on manipulation. The paper discusses the different techniques possible for implementing such a display and documents the implementation based on the Frustrated Total Internal Reflection (FTIR) technology.

MIES: a microarchitecture design tool

This paper describes MIES, a design tool for the modeling, visualization, and analysis of VLSI microarchitectures. MIES combines a graphical data path model and symbolic control model and provides a number of user interfaces which allow these models to be created, simulated, and evaluated.

Fuzzy modular multiplication architecture and low complexity IPR-protection for FPGA technology

The strong possibility of pirating, reengineering and over-deployment is a major impediment to the commercialization of IP-cores in the FPGA design environment. A mechanism for IP-protection based on public key bitstream encryption has previously been proposed. This paper describes a reasonable cost practical realization of the modular multiplication function required for the previously proposed system. A technique called fuzzy modular multiplication is employed to decrease the cost of modular squaring computations required for the public key exchange. An implementation using the Virtex-4 device from Xilinxreg is demonstrated to illustrate the low complexity cost. A refinement of the IP exchange scenario for the proposed IP-protection system is also included in this paper

Controlling on-chip inductive coupling of signal busses through swizzling

On-chip inductive coupling effects have been shown to depend directly on the overlap length between adjacent signal wires. This has major effect on global signal busses in high performance microprocessors. These busses are usually routed as a bundle containing a large number of signals traveling for long distances. In this paper, we propose a routing technique known as swizzling to control the inductive coupling effects between signal wires in global signal busses. The advantage of this technique is reducing the inductive coupling effects with zero area or routing resource cost.