Behnam Analui

A 130-nm CMOS 100-Hz–6-GHz Reconfigurable Vector Signal Analyzer and Software-Defined Receiver

A monolithic 100-Hz-6-GHz reconfigurable vector signal analyzer (VSA) and software-defined receiver (SDR), following a two-step up-down conversion heterodyne scheme with robustness to various wideband interference scenarios and local oscillator (LO) harmonic mixing, is presented. The 130-nm CMOS chip does not require external filters or baseband processing to reduce the effect of interferences or LO harmonics. The receiver has tunable gain from -67 to 68 dB in steps of 0.5 dB, and tunable bandwidth from 0.4 to 11 MHz in steps of 0.5 MHz. The receiver sensitivity at the maximum gain is - 82 dBm. A monolithic VSA/SDR enables various commercial and military wireless solutions.

Tunable Duplexer With Passive Feed-Forward Cancellation to Improve the RX-TX Isolation

The paper presents an approach that enables trading off the insertion loss versus isolation in the duplexer design. Specifically, the Insertion Loss (IL) of the duplexer filters is reduced by using low-order Bandpass Filters (BPF), while the transmitter (TX) to receiver (RX) isolation is improved using a feed-forward, passive, wideband, cancellation scheme. The proposed cancellation scheme is fully passive and hence the duplexer does not incur power consumption and noise penalties. The linearity of the proposed duplexer is very high limited only by the tunable passive components used in the design. A tunable duplexer prototype is demonstrated with TX-RX isolation better than 50 dB in both TX and RX bands (high band TX: 860-890 MHz, RX: 948-984 MHz; low band TX: 700-718 MHz, RX: 780-801 MHz). Tuning is achieved using digitally controlled switched capacitors with silicon on sapphire (SOS) switches resulting in high linearity.

A 130nm CMOS 100Hz–6GHz reconfigurable Vector Signal Analyzer and Software-Defined Receiver

A monolithic 100Hz–6GHz reconfigurable Vector Signal Analyzer (VSA) and Software Defined Receiver (SDR), following a two-step up-down conversion heterodyne scheme with robustness to various wide-band interference scenarios, is presented. The 130nm CMOS chip does not require external filters or baseband processing to reduce the effect of interferences or harmonics. A monolithic VSA/SDR enables various commercial and military wireless solutions.

A 50 MHz–6 GHz, 2 × 2 MIMO, reconfigurable architecture, software-defined radio in 130nm CMOS

A monolithic 50 MHz-6 GHz software-defined radio transceiver with two transmit (TX) and two receive (RX) channels to support 2 × 2 MIMO is implemented in 130nm CMOS. The transmitters and receivers frequency translation modes are reconfigurable to direct conversion or dual up-down conversion, featuring an on chip Q-enhanced 3 GHz 6-pole Chebyshev IF BPF in the dual conversion mode. The chip also includes two independent integrated wide-band frequency synthesizers for TX and RX paths to support Frequency Division Duplex (FDD) radios. Each frequency synthesizer has an integrated 50 MHz Direct Digital Synthesis (DDS) based reference into an integer-N PLL with integrated 3-tank VCOs, integrated loop-filter, and a zero-spur phase-frequency detector, to achieve low-spur and high resolution, simultaneously. The radio has >0 dBm TXP-1dB and >70 dB RX blocker tolerance (in-band and out of band) with <; 900 mW worst case total power consumption per transceiver channel.