Behzad Ebrahimi

A partial-SOI LDMOSFET with triangular buried-oxide for breakdown voltage improvement

In this paper, a near-triangular buried-oxide partial silicon-on-insulator (TB-PSOI) lateral double-diffused MOS field-effect transistor is proposed. The electric field and electrostatic potential in this structure are modified by the gradual buried-oxide thickness increase. The modification includes the addition of a new peak in the electric field in comparison to that of the conventional PSOI. To assess the efficiency of the proposed structure, its breakdown voltage is compared with that of conventional PSOI using two-dimensional simulations. A comparative study is performed in terms of silicon-film and buried-oxide layer thicknesses, drift region and buried-oxide layer lengths, and drift region doping concentrations. The study shows that under the same drain current, the breakdown voltage of TB-PSOI is nearly two times higher than its PSOI counterpart (108% improvement). Simulation results show that the three-stepped oxide layer closely follows the TB-PSOI structure with a breakdown voltage improvement of 96% compared to that of the PSOI structure.

Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage

In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved.

Process variation study of Ground Plane SOI MOSFET

In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.

G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems

G4-FET has attracted attention as an emerging device for the future generations of semiconductor industry. This paper is intended to propose a model representing the characteristics of G4FET device in order to perform circuit simulations. The modeling approach is established upon the neuro-fuzzy technique whose main strength is that they are universal approximators with the ability to solicit interpretable IF-THEN rules. The accuracy of the proposed model is verified by HSPICE circuit simulations.

A high speed subthreshold SRAM cell design

In this paper, we propose a subthreshold SRAM cell structure which can be read differentially. The main advantage of the cell is its high read current while the static noise margin and power consumption are reasonable. The cell is suitable for high performance applications where the speed is of prime concern. To assess the efficiency of the proposed cell, we compare its characteristics to three subthreshold SRAM cell structures recently introduced in the literature. The cells are implemented in both the bulk and SOI-FinFET technologies at the node of 32nm.

Low Standby Power and Robust FinFET Based SRAM Design

In this paper, we propose low power and robust 6T SRAM cells. The cells are based on the Vt-control of the cross-coupled inverters of the SRAM cell to reduce leakage power when SRAM is in the idle mode. Using the Vt-control method along with the built-in feedback leads to increasing the SNM. In comparison to a previous work, our schemes have a higher static noise margin (SNM) and lower standby power consumption. To assess the efficiency of the approach, HSPICE simulations in 45 nm and 32 nm FinFET technologies are used. The results show considerable improvements in terms of the standby power as well as the hold and read SNM. This suggests that the Vt-control method may be used for realizing low-standby power and robust SRAM.

Robust FinFET SRAM design based on dynamic back-gate voltage adjustment

In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed by dynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use an extra write driver which sets the desired back-gate voltages during this operation. This approach considerably increases the write margin. During the hold state, the back-gates are precharged to the supply voltage using an extra precharge circuit. This decreases the static power. Finally, we use nMOS switches to provide the optimum back-gate voltages during the read state. To minimize the area and power overheads, an instance of the circuitry is used for each column. The performance of the proposed technique is assessed using mixed mode device/circuit simulations for a physical gate length of 22 nm. The results show that the minimum operating voltage for six-sigma read and write yield is about 0.15 V lower than that of the recently proposed structures. In addition, the suggested SRAM shows significantly higher write margin and lower static power compared to the recently proposed structures. The minimum operating voltage of our proposed structure can be lowered down to 0.5 V through some work function tuning to balance the read and write stability. This minimum voltage is 0.1 V lower than the minimum operating voltage of the other structures with similar work function tunings.

Ground plane SOI MOSFET based SRAM with consideration of process variation

In this paper, the characteristics of static random access memory (SRAM) cells based on three silicon-on-insulator (SOI) device structures are studied using device simulations. The comparative study, which is performed in a 32nm standard CMOS technology, includes read static noise margin (read SNM), read current, and standby power. The structures include SOI with ground plane in substrate (SOI-GPS), SOI with ground plane in buried oxide (SOI-GPB), and SOI without ground plane (SOI-WGP). In addition, the variations of the SRAM characteristics due to channel length and thin-film thickness variations are investigated. The results show that the SOI-GPS structure is more resistant against the process variations when compared to the other two structures.

Realistic CNFET based SRAM cell design for better write stability

In this paper, a comparison between CNFET and Si-MOSFET SRAM cells at 32nm technology node are presented. The designs are based on predictive technology model (PTM) for the Si-MOSFET cell and CNFET Stanford model for the CNFET cell. For practical reasons, in the CNFET case, the substrate of the entire chip is considered to be one node. The effect of the voltage of this node on improving the overall characteristics of the CNFET cell is described. HSPICE simulation results show that CNFET has better performance compared to Si-MOSFET. Finally, the characteristics of the SRAM cell in the presence of fabrication imperfections of CNFET are studied. The write stability of CNFET SRAM is low because of the same current drive capability for both p- and n-CNFETs. For solving this problem, we weaken the pull up transistors by different channel length and CNT diameter with respect to n type transistors.

A robust and low power 7T SRAM cell design

In this paper, we propose a new seven transistors (7T) static random access memory (SRAM) cell that improves read stability and write ability of the conventional 6T SRAM cell. Separating read and write access transistors in this cell solves the conflict of access transistor sizing. Therefore, large write and small read access transistors are chosen leading to read stability and write ability enhancement. Moreover, by isolating the storage node from the read path, more improvement in the read stability is achieved. Single ended write operation in this cell leads to reduction in the number of write drivers. In order to further improve the write ability, a virtual ground for one of the inverters is used. This strategy weakens the positive feedback and enhances the write ability of the cell. HSPICE Simulations in 90 nm CMOS technology show 80% and 54.9% improvement for the proposed structure with respect to the conventional 6T cell in the read stability and write ability, respectively, at the supply voltage of 500 mV. Using the virtual ground in this design causes leakage power reduction for each cell by stacking effect. The virtual ground is shared among all the cells in a row in order to lower the SRAM block power and relax the area and power overhead of extra transistor that used. The HSPICE simulation results also show 12.35% improvement in the static power at the 500 mV supply voltage.