Beichao Zhang

14nm metal gate film stack development and challenges

As IC technology advances to 16/14 nm and beyond, FinFET architecture with advantage of excellent leakage performance becomes main stream in IC industry. However, it also brings big challenges for integration and processes due to its very aggressive structure and profile, CD shrinkage, shadow effect and gap-fill difficulty. In this work, atomic layer deposition (ALD) metal films, including TaN, TiN (TiSiN), TiAl and CVD W, were studied for replacement metal gate application. Challenges of step coverage & gap-fill, loading effect and tunable range of work function will be discussed and addressed. Thickness of high K capping layer (TiN or TaN), work function metal (TiN & TiAl), W barrier layer (TiN) all show strong effect on N/P MOS device Vt, and more than 300 mv tunable range of work function can be achieved. Besides, higher Al : Ti ratio process, interfacial special treatment between TiAl & W barrier TiN and different W process can lower down NMOS Vt. At the last, ALD and CVD process ensure good gap-fill performance when CD opening is larger than 5nm (aspect ratio is about 20∶1).

New applications and challenges of dielectric films at 14nm FinFET technology and beyond

With technology scaling towards 14nm and beyond, it becomes extremely difficult for conventional planar Field Effect Transistors (FETs) to suppress a short channel effect (SCE). FinFET technology is a promising candidate for further generation to overcome those issues. The gate of a FinFET wraps around the channel without heavy doping offers an improved electrostatic control to yield a tighter distribution and optimized CMOS circuit performance. Although a large part of well-established conventional CMOS processes can be used for FinFET fabrication, there are still a lot of new processes, applications and challenges that need to address, in order to meet stringent requirements of FinFET. In this paper, some new processes and applications of dielectric films at 14nm FinFET technology and beyond will be discussed, such as ALD BSG and PSG films for solid-state doping (SSD), flowable CVD (FCVD) film applied for STI and ILD gapfill, nitride films for self-aligned contact (SAC), etc. Furthermore, the preliminary evaluation result of those processes will also be discussed. Then, some challenges of those applications will be illustrated in details. Their improvement approaches of those dielectric films for different applications will be explored to address those challenges in order to meet fabrication requirements.

PMA effects on Al/HfO2 high-K PMOS capacitors

A two-step post-metallization annealing (PMA) process has been developed and it has demonstrated its significant benefit for high-k metal gate (HKMG) in reducing post chemical mechanical polish (CMP) Al corrosion defects. After metal gate CMP, samples are firstly treated with N2O plasma in a 400°C PECVD (plasma enhanced chemical vapor deposition) chamber for surface oxidization, before which the chamber has been cycled with pumping through N2 and noble gas mixture so as to remove moisture and/or particles on chamber wall. Then, N2O gas switched off and NH3/N2 mixture plasma turned on to nitridize the metal oxides. A multi-variable (e.g. Gas ratio, RF power, plasma treatment time, chamber pressure, etc.) statistical design of experiment (DOE) was performed to optimize processes for growing ultra-thin metal oxynitride (e.g. AlON, TiON, TaON, etc.) on top surface of the metal gate, which will work as the 2nd etch stop layer (ESL) as well. TEM results showed that metal has been dragged upwards desirably and 30~60Å self-aligned insulated film grown upon Al/HfO2 capacitor, but 50-100Å diffusing layer was also observed unavoidably, which may induce metal loss and lead to a higher electrical resistance. With PMA treatment, PMOS post-CMP corrosion defects have been reduced significantly by ~85% in isolated SRAM (Static Random Access Memory), by ~50% in dense area, and by ~75% at the gate boundary area. The correlation of IOFF v.s IDSAT and IDSAT v.s VDSAT (saturation voltage at sub-threshold regime) demonstrated a comparable performance with that of non-PMA process. In light of the findings from this study, a trade-off between defect reduction and N/O atom diffusion downward metal gate should achieve with further PMA optimization.

STI gap-fill optimization for advanced nodes

High aspect ratio process (HARP) and siconi process is widely used for STI gap fill in sub-65nm CMOS; it has good gap fill performance to high aspect profile. As IC technology advances to 28 nm and beyond, void free, high throughput and good uniformity STI gap fill has become a significant process challenge. In this work, we optimize AA etch profile and HARP process to improve STI gap fill. Use O3 or H2 plasma treat ISSG (in-situ steam generation) wafer surface to adjust the surface condition before STI cap. The result shows that after O3 plasma treatment HARP STI film has good film thickness uniformity and high film grow rate on ISSG wafer. From TEM cut and top down scan, void free and high throughput STI gap fill process has been achieved.

An optimized W process for metal gate electrode gap filling application

As IC technology advances to 16/14 nm and beyond, W film will not only be used to fill contact plug, but also act as electrode layer of replacement metal gate. High resistivity and W seam are two major concerns. W gap-fill capability is very good due to its conformal growth characteristic and easy transportation of reactive gases. However, the remaining opening of 16/14 nm FinFET replacement metal gate before W gap-fill is very narrow and sometimes has a re-entrant profile, which makes it very easy to form seams or voids. This paper reports an optimized W gap-fill process, which can fill in trenches of the aspect ratio > 30:1, with CD opening shrinking to less than 4nm. A NF3 etching back process is introduced, which can help to modulate the re-entrant profile and enlarge the gap-fill window. This D-E-D process can be easily extended to 10 nm technology node. Meanwhile, B2H6 post nucleation treatment is applied to lower W resistivity, down to 9.3 μΩ-cm at a thickness of 200 nm.

Study of grain size and polishing performance of aluminum film as metal gate electrode

Aluminum (Al) film has been implemented in semiconductor manufacturing such as gap fill in the metal gate trench. Al-induced crystallization and layer exchange processes showed great impact on grain size, and Al grain size was varied by deposition rate and temperature. We investigated grain size of Al deposited on different substrates of p-Si, PEOX and thermal oxide by DC magnetron sputtering. Grain size and film roughness were characterized by SEM and AFM. The film polishing result was correlative with grain size, smoothness and continuous Al film showed better CMP performance, while larger grain size was easier to be pulled out by CMP.

A simple model for ultra-low specific contact resistivity metal- interfacial layer -semiconductor contacts

A simple, physics-based model is developed for study of ultra-low specific contact resistivity metal-interfacial layer-semiconductor (M-I-S) contacts. Reduction in metal induced gap states (MIGS) density and Fermi level de-pinning in metal-semiconductor interface reduce the Schottky barrier height (SBH). Be coupled with electron transport model, the specific contact resistivity in different M-I-S system can be calculated.