Beilei Sun

Definitions of predictability for Cyber Physical Systems

With the recent proliferation of different types of Cyber Physical Systems (CPS), it is critically important to investigate the predictability of such systems. Along with functional correctness of the components, these systems must also ensure that timing and delay constraints of components are properly for the entire system to behave in a predictable manner in presence of various kinds of uncertainties. While the functional correctness of the CPS components has been investigated in the past, very little is available about the timing issues. The objective of this paper is to conduct an investigation of key issues involved to ensure the predictability of the system, introduce rigorous definitions of performance parameters, and propose metrics for their evaluation and analyze their suitability to be used in the presence of uncertainties in which CPS operate. The results are expected to provide greater insight into the time critical behavior of CPS components.

Texture-Directed Mobile GPU Power Management for Closed-Source Games

Power consumption and battery life constrain the developments of the mobile platforms. Among the mobile applications, games are the most demanding applications in terms of both computational cost and consumed energy. The power consumption spent on GPU to accelerate the rendering speed keeps increasing rapidly. Most of the GPU power saving techniques using the prediction-based GPU DVFS policies. We propose the Texture-Directed Mobile GPU DVFS policy based on the observation that GPU workloads and texture operations in CPU are strongly positively correlated when playing games. The proposed policy utilizes the texture operations collected from the front-end of the graphic pipeline to scale the GPU frequency. The evaluation results show that, compared with the prediction-based policy, our policy saves more power in the tested games with competitive performance. Up to 43.75% GPU power consumption is saved in the games whose scenes change drastically. About 7.16% power is saved on average in games whose scenes change gently.

FCM: Towards Fine-Grained GPU Power Management for Closed Source Mobile Games

Contemporary mobile platforms employ embedded graphic processing units (GPUs) for graphics-intensive games, and dynamic voltage and frequency scaling (DVFS) policies are used to save energy without sacrificing quality. However, current GPU DVFS policies result in unnecessary power waste due to defective workload estimations of embedded GPUs during game play. In this paper, we propose the Frame-Complexity Model (FCM), a fine-grained estimation of the GPU workload in a game frame, to quantify the GPU workload with the real runtime demand for GPU computing resources of a game frame. In FCM, three constituents of a game frame (i.e., structure, textures and computation) are quantified without modification of mobile games. Preliminary experiments show that, compared with the default policy, the FCM-directed GPU DVFS policy can reduce more power consumption of games (11.3% to 25.8%) with good Quality of Service (QoS).

Automatic frame rate-based DVFS of game

The rapid development of mobile games highlights the power consumption problem in the mobile platform. Most of the power saving techniques use the prediction-based dynamic voltage frequency scaling (DVFS) scheme. However, the prediction could be inaccurate resulting from the frequent interactions of user when playing games. We have observed that frame rate is near-linear to CPU frequency, but there is a bottleneck, frame rate will not increase as CPU frequency increases when CPU frequency reaches this threshold. Moreover, previous research has shown that utilizing the information of game state can reduce the influence of game interactive characterization to DVFS policy. We explore a method to automatically detect the game state. We propose the Automatic Frame Rate-Based DVFS policy, which can learn the threshold of frame rate online and utilize the information of game state and frame rate to scale the frequency without prediction. Our evaluation result shows that, compared with the prediction-based Android default Interactive DVFS policy, our policy saves more power in all the testing games. Up to 15.2% more power can be saved by Automatic Frame Rate-Based DVFS policy.

Behavior-Aware Integrated CPU-GPU Power Management for Mobile Games

Since game applications have spilled over on the modern mobile platforms equipped with Multiprocessor Systemon-Chips and highlighted the power consumption and battery life problem of these platforms, reducing the game power for mobile devices becomes meaningful. The design of independent CPU-GPU power managements in contemporary platforms results in power consumption waste due to the failure of consideration of CPU-GPU interaction and game workload behaviors. Through analyzing the Application-Operating System (APP-OS) interaction and CPU-GPU interaction, we extract the system-call information and OpenGL API information to characterize the game workload in a low-complexity way. In this paper, based on identifying the game workload behavior and performance bottleneck, we propose a behavior-aware integrated CPU-GPU power management approach for mobile games. We also implement our power saving policy in the real platform, where the evaluation results show that our behavior-aware policy can significantly reduce power and improve game performance. Our policy provides 18% and 5% higher power-efficiency on average compared with the current policy used in our platform and the state-of-the-art policy respectively.

KUMMS: optimising DRAM locality with Kernel-user behaviours

DRAM accesses from operating system and user applications are analysed together in the existing researches, which try to improve the DRAM efficiency. In this paper, we find that Kernel and user perform different behaviours while accessing DRAM and interfere with each other greatly. Based on the observations, we divide the DRAM into Kernel-space, user-space and reserved-space. Different policies are designed for different spaces. We also introduce a new lock algorithm for the buddy system to deal with the page requests contentions in the multicore system. Experimental results show that the DRAM locality are averagely improved by more than 10% in the bank:row:column scheme and about 5% in the row:bank:column scheme. The improvements of RBH increase the system throughput without affecting the fairness, and averagely reduce the execution times of different benchmarks by 7.00% and 5.20% in the bank:row:column scheme and row:bank:column scheme, respectively.

Kernel-User Space Separation in DRAM Memory

Performance of software is increasingly restricted by the Memory Wall instead of CPU. Many studies focus on alleviating the DRAM latency by improving the row-buffer hit rate. But most of them treat the Kernel and User equally. Data used by Operating System and User applications spread in different rows of the same bank, leading to the contentions for the row-buffer when they access the bank successively. We find that contentions between Kernel and User make up of a great proportion of all the row-buffer misses. To alleviate the contentions between Kernel and User, we divide the united DRAM memory space into Kernel-Space and User-Space. A new page-allocation-system, the K/U-Aware page-allocation-system, is proposed to manage Kernel-Space and User-Space in DRAM memory in different address mapping schemes of DRAM memory controller. In the new system, pages are allocated from different spaces according to applicants (Kernel or User). Sizes of the two spaces increase and decrease dynamically as required. For benchmarks in PARSEC suites, the proposed system reduces the contentions of Kernel and User effectively, producing significant improvements of row-buffer hit rate. The execution time is reduced by 9.45% (max. 20.45%) and 6.51% (max. 18.05%) respectively in two typical address mapping schemes.

A Thread Behavior-Based Memory Management Framework on Multi-core Smartphone

Memory management systems have significantly affected the overall performance of modern multi-core smartphone systems. Android, as one of the most popular smartphone operating systems, adopts a global buddy system with the FCFS (first come, first served) principle for memory allocation, and releases requests to manage external fragmentations and maintain the memory allocation efficiency. However, extensive experimental study on thread behaviors indicates that memory external fragmentation is no longer the crucial bottleneck in most Android applications. Specifically, a thread usually allocates or releases memory in bursts, resulting in serious memory locks and inefficient memory allocation. Furthermore, the pattern of such bursting behaviors varies throughout the life cycle of a thread. The conventional FCFS policy of Android buddy system fails to adapt to such variations and thus suffers from performance degradation. In this paper, we propose a novel memory management framework, called Memory Management Based on Thread Behaviors (MMBTB), for multi-core smartphone systems. It adapts to various thread behaviors through targeted optimizations to provide efficient memory allocation. The efficiency and effectiveness of this new memory management scheme on multicore architecture is proved by a theoretical emulation model. Our experimental studies on the real Android system show that MMBTB can improve the efficiency of memory allocation by 12%-20%, confirming the theoretical analysis results.

Behavior Gaps and Relations between Operating System and Applications on Accessing DRAM

Detailed analyses of the behaviors of operating system and applications are significant for taking full advantage of the precious hardware resources and improving performance. This paper focus on their DRAM access behaviors based on access proportion and row-buffer miss ratio (RBM). The access proportions of Kernel and User vary greatly in different stages throughout the lifetime of a process. Most of the row-buffer misses are caused by the one having higher access proportion. By analyzing the RBM series through ARMA model, we found that Users DRAM accesses only have short-term influences on its behavior, while the Kernels influences are relatively deeper. The ARMA model for the RBM series is able to predict the future RBMs, which are profound basis to schedule the DRAM access commands. The results of Gaussian Fitting show that Kernel and User are tightly correlated on accessing DRAM, especially in the steady stage and the end stage of a processs life cycle. Based on this close relation, it is possible to estimate the DRAM access behaviors of the other one according to the one whose behaviors have been known. System-calls that obviously affect the access proportions and RBMs are also revealed in this paper.

Application-aware group scheduler for Android

Modern multi-core processors propose new cache management challenges (more cache conflicts and misses) due to the subtle interactions of simultaneously executing processes sharing on-chip resources. To address this issue, thread group scheduling scheme that cluster threads with high sharing cache as one group to schedule has been proposed. It has led to numerous academic and industrial attentions. However, by analyzing the programming model of Android which account for a large and increasing fraction of operating system of multi-core smart phones, we find it may be unacceptable for numerous interactive applications since previous scheduling works may cause the terrible response time and directly bring an awful user experience. In order to reduce cache competitions while improving applications response time, we present an application-aware group scheduler (AGS) whose key idea is to adopt a thread group scheduling scheme to partition current running applications threads into one group and give each thread a fair chance to occupy CPU time. We implement AGS on practical hardware running a real Android operating system. The results show that our proposed scheduler can improve performance from different parameters while keeping system fairness, which reduces 3.2% in cache miss rate, 5.5% in response time, 5.3% in data cache (D-Cache) misses and 2.5% in instruction cache (I-Cache) misses to the maximum extent.