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Grid Computing Implementation in Ad Hoc Networks

The development of ubiquitous computing and mobility opens challenges for implementation of grid computing in ad hoc network environments. In this paper, a new grid computing implementation for ad hoc networks is proposed. The proposed addition of the ad hoc network protocols suite offers an easy and effective way to exploit the computing power of the network nodes. The model is implemented in the NS-2 network simulator providing the possibility to investigate its performances and tune the network grid parameters.

Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored

In this paper we explore a hierarchical memory architecture that simplifies the WCET prediction of tasks. Instead of using cache memories for speeding up code execution, we propose to use hierarchical memories that are similar to scratchpad memories. These memories are filled by explicit prefetch operations that are executed in synchrony with program execution. The instructions respectively the data that determine both the content and the timing of the operations that perform the memory transfers between the different memory levels are computed at code-generation time. The paper describes the overall system and memory architecture, and design choices for explicitly controlled time-predictable hierarchical memory architectures.

A TDMA-Based arbitration scheme for mixed-criticality multicore platforms

In mixed-criticality systems, applications of different criticality levels share the same computing platform. To avoid spatial and temporal interference of the applications, the computing platform must implement measures for spatial and temporal isolation. In this paper we show how the enhancement of a static, TDMA-based memory arbiter by a second, dynamic arbitration layer facilitates the interference-free integration of mixed-criticality applications with different performance requirements. This paper compares the performance tradeoffs of the new dual-layer arbiter and a COTS arbiter and evaluates the performance of a hypervisor running on a platform with this dual-layer arbiter.

A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking

Trustable Worst-Case Execution-Time (WCET) bounds are a necessary component for the construction and verification of hard real-time computer systems. Deriving such bounds for contemporary hardware/software systems is a complex task. The single-path conversion overcomes this difficulty by transforming all unpredictable branch alternatives in the code to a sequential code structure with a single execution trace. However, the simpler code structure and analysis of single-path code comes at the cost of a longer execution time. In this paper we address the problem of the execution performance of single-path code. We present a new cache organization that utilizes the principle of locality of single-path code to reduce cache miss latency and cache miss rate. The proposed cache memory architecture combines cache prefetching and cache locking, so that the prefetcher capitalizes on spatial locality while the locker makes use of temporal locality. The demonstration section shows how these two techniques can complement each other.

New algorithms for efficient scheduling in Grid Ad-Hoc networks

The number of devices that can be connected wirelessly in an ad hoc network has increased greatly. Implementation of Grid computing in such environment would create a high processing power by aggregation of processing power of nodes. For implementation of Grid systems on ad-hock wireless networks we propose a new layer called Ad Hoc Grid Layer (AHGL). This layer contains all necessary services for Grid implementation. Considering a dynamic nature of the ad hoc network, it is very important for job execution to select and allocate appropriate processing node. In Grid computing this work is done by the service called scheduler. Using the wired Grid scheduling algorithms for assigning jobs in a Grid ad hoc network is not straightforward. Hence, in this paper we propose new scheduling algorithms which optimize time needed to transmit and execute jobs in Grid environment created on an ad hoc network. Simulation results show that the new proposed scheduling algorithms provide better performances in comparison with application of scheduling algorithms used in wired Grid.

Constructing Time-Predictable MPSoCs: Avoid Conflicts in Temporal Control

Todays multicore system architectures are too complex. They are not ready for use in highly dependable, safety-critical applications. We show that a system and component design that avoids conflicts in the temporal control of computations and actions allows us to build less complex multi-core systems whose temporal behavior is easy to predict. At the multi-core system level this can be achieved by using highly autonomous cores and a time-triggered NoC for communication. At the level of single cores the elimination of input-dependent control flow of software and the use of software-controlled memory hierarchies contribute to this aim.

Using a Local Prefetch Strategy to Obtain Temporal Time Predictability

Todays embedded systems are considering cache as inherent part of their design. Unfortunately, cache memory behavior heavily depends on the past references which model a large execution history and makes WCET analysis impractical. This paper presents a novel prefetch memory mechanism that simplifies the prediction of cache hits/misses because the memory access times are independent of the execution history. We use local prefetching into on-chip memory together with a custom-designed prefetch controller instead of cache memories to provide for time-predictable memory accesses. To be competitive in code execution time, our approach relies on a special organization of main memory and on a modified compiler that generates code layouts to allow for parallel prefetching from different memory banks. The proposed solution is still in a conceptual phase. The paper discusses design decisions and parameters to be explored.

Best Practice for Caching of Single-Path Code

Single-path code has some unique properties that make it interesting to explore different caching and prefetching alternatives for the stream of instructions. In this paper, we explore different cache organizations and how they perform with single-path code.

Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy

Deriving the Worst-Case Execution Time (WCET) of a task is a challenging process, especially for processor architectures that use caches, out-of-order pipelines, and speculative execution. Despite existing contributions to WCET analysis for these complex architectures, there are open problems. The single-path code generation overcomes these problems by generating time-predictable code that has a single execution trace. However, the simplicity of this approach comes at the cost of longer execution times. This paper addresses performance improvements for single-path code. We propose a time-predictable memory hierarchy with a prefetcher that exploits the predictability of execution traces in single-path code to speed up code execution. The new memory hierarchy reduces both the cache-miss penalty time and the cache-miss rate on the instruction cache. The benefit of the approach is demonstrated through benchmarks that are executed on an FPGA implementation.

Aligning single path loops to reduce the number of capacity cache misses

In this paper we address the problem of improving the instruction cache performance for single-path code. The properties of single-path code allow us to align single-path loops within the cache in order to reduce the number of cache misses during the loop execution. We propose an algorithm that categorizes loops in a simple way so that the loops can be aligned and NOP instructions can be inserted to support this loop alignment. Our experimental results show the predictability for cache misses in single-path loops and demonstrate the benefit of the single-path loop alignment.