Béla Fehér

Using run-time reconfiguration for fault injection in hardware prototypes

In this paper, a new methodology for the injection of single event upsets (SEU) in memory elements is introduced. SEUs in memory elements can occur due to many reasons (e.g. particle hits, radiation) and at any time. It becomes therefore important to examine the behaviour of circuits when an SEU occurs in them. Reconfigurable hardware (especially FPGAs) was shown to be suitable to emulate the behaviour of a logic design and to realise fault injection. The proposed methodology for SEU injection exploits FPGAs and, contrarily to the most common fault injection techniques, realises the injection directly in the reconfigurable hardware, taking advantage of run-time reconfiguration capabilities of the device. In this case, no modification of the initial design description is needed to inject a fault, that results in avoiding hardware overheads and specific synthesis, place and route phases.

A full-parallel digital implementation for pre-trained NNs

In many applications the most significant advantages of neural networks come mainly from their parallel architectures ensuring rather high operation speed. The difficulties of parallel digital hardware implementation arise mostly from the high complexity of the parallel many-multiplier structure. This paper suggests a new bit-serial/parallel neural network implementation method for pre-trained networks. The method makes possible significant hardware cost savings. The proposed approach-which is based on the results of a previously suggested method for efficient implementation of digital filters-uses bit-serial distributed arithmetic. The efficient implementation of a matrix-vector multiplier is based on an optimization algorithm which utilizes the advantages of CSD (canonic signed digit) encoding and bit-level pattern coincidences. The resulting architecture performs full-precision computation and allows high-speed bit-level pipeline operation. The proposed approach seems to be a promising one for FPGA and ASIC realization of pre-trained neural networks and can be integrated into automatic neural network design environments. However, these implementation methods can be useful in many other fields of digital signal processing.

Acoustic Source Localization Fusing Sparse Direction of Arrival Estimates

This paper proposes a wireless sensor network based acoustics source localization and tracking system. Each individual node has a special purpose sensor board with four acoustic channels and a digital compass enabling direction of arrival (DOA) estimation of acoustic sources. Upon detecting a source of interest, the sparsely deployed sensor nodes report their DOA estimates to the base station that fuses the data for accurate localization. Due to the widely distributed sensing and the novel sensor fusion technique, the method can handle multiple measurement errors prevalent in reverberant environments. The paper presents the overall architecture of the system, as well as that of the advanced sensor board. Furthermore, it describes the DOA estimation algorithm and the applied middleware services for coordinated sensing and communication, introduces the sensor fusion algorithm and presents a detailed error analysis

Molecular Docking on FPGA and GPU Platforms

Molecular docking is an important problem of bioinformatics aiming at the prediction of binding poses of molecules. Auto Dock is a popular, open-source docking software applying a computationally expensive but parallelizable algorithm. This paper introduces an FPGA-based and a GPU-based implementation of Auto Dock and shows how the original algorithm can be effectively accelerated on the two different platforms. According to test runs, both implementations achieve significant speedups over Auto Dock running on a single CPU core and on a quad-core system. Comparison of the two implementations proves that many-core graphics processing units can be a real alternative to FPGAs in the field of high performance computing.

Dependability analysis: a new application for run-time reconfiguration

The probability of faults, and especially transient faults, occurring in the field is increasing with the evolutions of the CMOS technologies. It becomes therefore crucial to predict the potential consequences of such faults on the applications. Fault injection techniques based on the high level descriptions of the circuits have been proposed for an early dependability analysis. In this paper, a new approach is proposed, based on emulation and run-time reconfiguration. Performance evaluations and practical experiments on a Virtex development board are reported.

Hardware Accelerated Molecular Docking: A Survey

Hardware acceleration is the general concept of applying a specialized hardware for a given problem instead of an ordinary CPU in order to get lower processing time. General purpose CPUs can be considered as a totally general platform suitable for executing virtually any software or algorithm. Application specific accelerators have a custom architecture that fits the needs of a certain family of algorithms. As a consequence, they are able to outperform CPUs by orders of magnitude in a special application area but they are unfit for other, more general tasks. In contrast to normal CPUs, which are essentially serial machines executing instructions sequentially, hardware accelerators use parallel architectures which allow them to exploit the parallelism available in the given application by performing independent operations simultaneously.

High-performance timing-driven rank filter

This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.

High performance visibility testing with screen segmentation

There are two factors determining the performance a 3D accelerator can achieve: the available computational power and the available memory bandwidth. In embedded systems, these resources are even more limited then in desktop environments, thus the efficiency of the hardware architecture and the exploitation of the logic resources become even more important. Most resources are wasted at the visibility testing process: traditional implementations require a lot of bandwidth, and process pixels which are not visible on the final image. By segmenting the screen, the presented architecture can use high performance, on-chip buffers to lower memory requirements and to provide high performance. The order of the processing guarantees that only those colors are computed, which are truly visible. The modular architecture allows satisfying different requirements: a trade off can be made between the number of processing units and performance.

LOGSYS: A simple tool for complex student projects

The LOGSYS Development Environment is used as a versatile tool in different levels of the education of the B.Sc. and M.Sc. Embedded System courses. The motivation at the introduction was to provide an affordable platform to every student, which offers compatibility with the existing industry standard solutions, while can support practical design work from the basic examples, through simple systems, up to the modern model based methodologies. The main components of the solution include the FPGA board, the development cable and the user application. The USB powered compact board makes possible its usage during class work, allowing direct experience on the presented topics. The LOGSYS tool set is compatible with the major Xilinx software components, like ISE, EDK, ChipScope, and offers the usability of MATLAB Simulink/System Generator and LabVIEW FPGA Module. These two later model based methodologies are very useful in case of the DSP and control type applications.

High Performance Timing-Driven Rank Filter

This paper presents an FPGA implementation of a high performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoff between complexity and clock speed. By maximizing the operating frequency the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.