Ben Johnson

An Orthogonal Current-Reuse Amplifier for Multi-Channel Sensing

We demonstrate a micropower low-noise CMOS amplifier array that reuses bias current to improve the fundamental noise-power tradeoffs of fully-differential amplifier designs. The presented circuit implements current-reuse by stacking the differential input pairs of four amplifiers. The output drain currents of each channels differential pair are used as the tail currents for the differential pairs of the succeeding channel. Orthogonal current-reuse improves the noise and power tradeoff by sharing bias devices to conserve headroom. With four channels (n = 4), there are 16 unique output currents (2n) from the stack, each of which is a linear combination of the four inputs. Amplified versions of the original input signals are reconstructed by appropriately combining the small-signal output currents in output stages that operate at much lower bias currents. With an input-referred noise of 3.7 μVrms and a bandwidth of 19.9 kHz, a single channel achieves a noise efficiency factor (NEF) of 3.0. Amortizing the bias current across the amplifiers four channels yields an effective NEF of 1.64. The total power consumption is 15.6 μW, or 3.9 μW per path from a 1.5 V supply. Orthogonal biasing suppresses crosstalk between the channels, providing an isolation of 40 dB under 3-σ mismatch. The implemented circuit was fabricated in a standard 130 nm CMOS process and occupies an area of 0.125 mm2. The proposed technique is useful for a variety of applications ranging from low-power neural recording arrays to multiphase radio baseband amplifiers.

A Wideband Receiver With Resonant Multi-Phase LO and Current Reuse Harmonic Rejection Baseband

In this work we present an architecture for a low power SDR which draws on techniques from both narrowband low power radios and recent work in SDRs. The receiver consists of a wide tuning-range passive mixer, driven with resonant non-overlapping LO drive combined with a noise-power optimized multi-path baseband amplifier. LO generation circuitry drives the mixer with an 8-phase, 12.5% duty cycle LO, but does so directly from complementary LC-tank VCOs in order to resonate out the gate capacitance of the mixer. A capacitor sharing technique on the baseband side of the mixer doubles the RX frequency range of the 8-phase clock at no added cost in power or performance, while achieving a NF as low as 7 dB. The 1.8 mW low noise baseband amplifier reuses the bias current of its four input channels while rejecting the 3rd/5th harmonics by >34 dB. The receiver consumes 10–12 mW (including VCOs, pulse generation and baseband) over a frequency range of 0.7–3.2 GHz with a 1.3 V supply.

A low-power orthogonal current-reuse amplifier for parallel sensing applications

We demonstrate a low-noise CMOS amplifier array using orthogonal bias current-reuse to improve fundamental noise-power trade-offs. The architecture presented uses stacking to share bias current among the input differential pairs of four amplifiers. By using the output drain currents of each differential pair as tail currents for the next stage, we save bias current. By arranging the stacked differential pairs appropriately, we generate 16 output currents that encode the original inputs in a linearly independent (orthogonal) fashion. These outputs are then recombined in much lower power output stages to reconstruct amplified versions of the inputs. Our design was built in standard 130nm CMOS and has a noise efficiency factor (NEF) of 2.7, close to the lowest published for a differential amplifier. However, amortizing bias current across the 4 parallel amplifier paths in the NEF calculation yields an effective NEF of 1.54. The input-referred noise ranges from 14.5 ßVrms to 17.4 /iVrm. between amplifiers in the stack over bandwidths of 426 kHz to 530.2 kHz while consuming a total power of 19.6 μ-W, or 4.9 μ\¥ per path. Orthogonal biasing avoids cross-talk between stacked amplifier paths, providing isolation of 37 dB or better.

A 768-Channel CMOS Microelectrode Array With Angle Sensitive Pixels for Neuronal Recording

This paper presents a CMOS sensor array with a 768 low-noise recording sites for neural recording with 2048 intercalated angle-sensitive pixels for optical read-out. The array is highly scalable because of electrode-level digitization with serial data stream-out. The front-end amplifiers use chopping to reduce flicker noise and achieve an input-referred noise of 4.1 μVrms over a 3.6 kHz bandwidth while occupying an area of only 800 μm2. Digitization is performed using a distributed ramp ADC that samples every sensor site at 10 kHz. The electrodes have a 50 μm pitch and are plated with platinum to increase the interface capacitance and ensure biocompatibility. The sensor array is used to refocus a lenless image and to record neural spiking and local field potentials from a mouse olfactory bulb slice.

An on-chip 72×60 angle-sensitive single photon image sensor array for lens-less time-resolved 3-D fluorescence lifetime imaging

We present a 72×60, angle-sensitive single photon avalanche diode (A-SPAD) array, able to perform lens-less 3-D fluorescent lifetime imaging. A-SPAD pixels are comprised of (1) a SPAD to resolve precise timing information, reject high-powered UV stimulus, and map the lifetimes of different fluorescent sources and (2) integrated diffraction gratings over the SPAD to extract the incident angle of light, enabling 3-D localization at a micrometer scale. The chip integrates pixel-level counters and shared timing circuitry, and is implemented in unmodified 180nm CMOS.

Putative Partners: Protecting Couples from the Consequences of Technically Invalid Domestic Partnerships

In 2006, Lena Velez sought to end her fifteen-year relationship with Krista Smith.1 Velez filed an action in the Mendocino Superior Court to officially dissolve her domestic partnership and requested partner support, continued health coverage, and a division of her and her partners property and 2 assets. There was only one problem with Velezs request: neither she nor her partner had ever registered a domestic partnership with the state of California. Instead, Velez and Smith had only registered their partnership with the City and County of San Francisco.3 This is important because of the differences in benefits offered by registration with the State of California and registration with the City and County of San Francisco. Without a valid state registration, Velez would not be able to receive a share of the property acquired by the couple during their relationship and would be ineligible for continued health insurance coverage.

A <12mW, 0.7–3.2GHz receiver with resonant multi-phase LO and current reuse harmonic rejection baseband

We present a wide tuning range passive mixer-first receiver with resonant non-overlapping LO drive and noise-power optimized multi-path baseband amplifier. The receiver consumes 10-12mW (including VCOs, pulse generation and baseband) over a frequency range of 0.7-3.2GHz with a 1.3V supply. An LO generation architecture generates a 12.5% duty cycle resonant clock from standard complementary LC-tank VCOs. A capacitor sharing technique on the baseband side of the mixer doubles the RX frequency range of the 8-phase clock, achieving a NF as low as 7dB. The 1.8mW low noise baseband amplifier reuses the bias current of its four input channels while rejecting the 3rd/5th harmonics by >;34dB.

A scalable CMOS sensor array for neuronal recording and imaging

We present a CMOS sensor array with 768 low-noise recording sites for neural recording with 2,048 intercalated angle-sensitive pixels (ASP) for optical read-out. The design is highly scalable due to electrode-level digitization with serial data stream-out. The front-end amplifiers use chopping to reduce flicker noise and achieve an input-referred noise of 4.1µVrms over a 4.2kHz bandwidth while occupying an area of only 800µm2. Digitization is performed by using a distributed ramp ADC that samples every sensor site at 10kHz. Each electrode is plated with platinum to increase the interface capacitance and ensure biocompatibility. The large number of electrodes, 50µm electrode-pitch, and combined optical information will enable sophisticated optogenetic neurophysiological research on a chip.

A 72 × 60 Angle-Sensitive SPAD Imaging Array for Lens-less FLIM

We present a 72 × 60, angle-sensitive single photon avalanche diode (A-SPAD) array for lens-less 3D fluorescence lifetime imaging. An A-SPAD pixel consists of (1) a SPAD to provide precise photon arrival time where a time-resolved operation is utilized to avoid stimulus-induced saturation, and (2) integrated diffraction gratings on top of the SPAD to extract incident angles of the incoming light. The combination enables mapping of fluorescent sources with different lifetimes in 3D space down to micrometer scale. Futhermore, the chip presented herein integrates pixel-level counters to reduce output data-rate and to enable a precise timing control. The array is implemented in standard 180 nm complementary metal-oxide-semiconductor (CMOS) technology and characterized without any post-processing.

A Polar Symmetric CMOS Image Sensor for Rotation Invariant Measurement

We present a CMOS image sensor for efficient capture of polar symmetric imaging targets. The array uses circular photodiodes, arranged in concentric rings to capture, for example, diffraction patterns generated by optically probing a revolving MEMS device. The chip is designed with a vacant, central spot to facilitate the easy single-axis alignment of the probing illumination, target device, and detector. Imaging of high-speed rotation (>1 kfps) is made possible by dividing the array into multiple concentric bands with sectorwise addressing control. We introduce a global shutter pixel reset scheme that reduces fixed pattern noise by being insensitive to parasitic capacitance from variable routing. We demonstrate the sensors capability to measure the rotation angle with a precision of 32 μrad and the rotation rates up to 300 rpm. Finally, we demonstrate the concept of a compact optical metrology system for continuous inertial sensor calibration by imaging the diffraction pattern created by a commercial MEMS accelerometer probed by a red laser shone through the axis of symmetry of the image sensor.