Benjamin Arazi

Message Authentication in Computationally Constrained Environments

RFID and wireless sensor networks exemplify computationally constrained environments, where the compact nature of the components cannot support complex computations or high communication overhead. On the other hand, such components should support security applications such as message integrity, authentication, and time stamping. The latter are efficiently implemented by hash message authentication codes (HMAC). As clearly stated in the literature, current approved implementations of HMAC require resources that cannot be supported in constrained components. An approach to implement a compact HMAC by the use of stream ciphering is presented in this paper.

DNA-based random number generation in security circuitry

DNA-based circuit design is an area of research in which traditional silicon-based technologies are replaced by naturally occurring phenomena taken from biochemistry and molecular biology. This research focuses on further developing DNA-based methodologies to mimic digital data manipulation. While exhibiting fundamental principles, this work was done in conjunction with the vision that DNA-based circuitry, when the technology matures, will form the basis for a tamper-proof security module, revolutionizing the meaning and concept of tamper-proofing and possibly preventing it altogether based on accurate scientific observations. A paramount part of such a solution would be self-generation of random numbers. A novel prototype schema employs solid phase synthesis of oligonucleotides for random construction of DNA sequences; temporary storage and retrieval is achieved through plasmid vectors. A discussion of how to evaluate sequence randomness is included, as well as how these techniques are applied to a simulation of the random number generation circuitry. Simulation results show generated sequences successfully pass three selected NIST random number generation tests specified for security applications.

Double-precision modular multiplication based on a single-precision modular multiplier and a standard CPU

The author considers the case where double-precision modular multiplications need to be performed by a device containing a custom IC that provides for a single-precision modular multiplication. The method presented is obviously extended to multiplying (k*n)-bit operands using an n-bit modular multiplier, for the case where k is a power of 2. Whereas multiprecision modular multiplication is simply executed using an available single-precision modular multiplier which provides external division services, the existence of these services is not assumed in the process presented, as the operation carried by the available modular multiplier is not necessarily based on proper division. The process is controlled by a standard CPU which also performs some simple calculations. >

Using flat concurrent Prolog in system modeling

The flat concurrent Prolog (FCP) language, which enables the implementation of synchronization through data flow, communication through shared variables, parallelism through the reduction of the AND components in the clauses body, and indeterminacy through guarded commands, is discussed. It is shown that FCP, used in conjunction with Petri net methods, forms a powerful tool in the modeling of parallel systems that involve concurrency. The simulation of systems represented by various types of Petri nets is achieved using the reduction process of FCP. AND parallelism supports free competition among conflicting enabled transitions. A structural analysis of systems is provided using the metaprogramming technique. >

Concurrent logic programming as a hardware description tool

The possibility of developing hardware description languages (HDLs) based on the principles of logic programming is discussed. The specific logic programming language used to demonstrate this possibility is Flat Concurrent Prolog (FCP). It is shown explicitly how FCP naturally satisfies the commonly accepted fundamental requirements of a hardware description language. It is then demonstrated how FCP overcomes known disadvantages of the highly acclaimed VHDL. Some other parallel logic programming languages beside FCP are also presented briefly, and the possibility of using them for hardware description is discussed. >

On primality testing using purely divisionless operations

Based on its definition, it appears that primality testing should inherently involve a division operation. Even the popular primality testing procedure which involves modular exponentiations has a division essence. Montgomery arithmetic facilitates modular exponentiation without divisions, provided that certain precalculations which involve proper divisions are first performed. In primality testing these precalculations have to be redone for each number whose candidacy for primality is tested. It is shown in this paper how primality testing can still be based on Montgomery arithmetic, such that no operation, including the precalculation, involves proper divisions. That is, it is shown that a complete primality testing process can be based on divisionless operations only

Architectures for exponentiation over GD(2/sup n/) adopted for smartcard application

Two exponentiation circuits are proposed. Using the fact that squaring is a linear operation over GF(2/sup n/), a time-space tradeoff in smartcard-based circuitry is presented. It is shown how multiplication is performed by a single shift, based on replacing the public key alpha /sup a/ in GF(2/sup n/) by its minimal polynomial. Other considerations, related to structure regularity and the possible use of dynamic shift registers, are also treated. >

On the synthesis of de-Bruijn sequences

A way of designing de-Bruijn sequence generators is presented. The design is based on modifying a generator consisting of a serial connection of two m-sequence generators. If m and n are the sizes (in stages) of the two generators involved, the calculations performed during the design consist mainly of : (1) Raising a root of a certain polynomial to the power 2 m. (2) Solving a set of 2n linear equations. The first operation is known to be simple to execute. 1. INTRODUCTION

The optimal burst-error correcting capability of the codes generated by ƒ(x) = (xp + 1)(xq + 1)/(x + 1)

Considerable attention has been devoted in the literature to the possible use of ƒ( X ) = ( X p + 1)( X q + 1)/( X + 1), where ( p, q ) = 1, as a generator polynomial of burst-correcting cyclic codes, owing to the extremely simple hardware implementation of both encoder and decoder, and the flexibility in choosing suitable codes. The problem of finding a relation among p, q and a certain b , such that the code generated by ƒ( X ) corrects error bursts of length b or less, has been solved in a number of ways. A complete optimal solution is presented here; i.e., it is shown how the maximum possible value of b can be determined when p and q are given. In most cases, the values obtained from the presented solution outperform those known hitherto. For b > 28 and for relatively long blocks, the presented codes are more efficient than the most efficient codes known. The probability is also found of detecting error bursts whose length exceeds the maximum correctable.

Random number generation for DNA-based security circuitry

Background Traditional silicon-based circuits have an inherent issue in that looking at the physical layout of their components can reproduce them. In order to help alleviate this problem, DNA computing, which borrows from the fields of biochemistry and molecular biology, can be used to produce dynamic computing systems. Full-blown DNA computing will require a paradigm shift in circuitry design. As a first step, we present a technique for random number generation incorporating technologies currently in use.