Benjamin Pfundt

Designing and manufacturing of real embedded multi-core CPUs: A holistic teaching approach in computer architecture

How to teach students current computer architecture? This is an important question in our modern world, where the market of embedded parallel processors is continuously growing. In every compact device today, such as smart phones and tablets, small and powerful multi-core architectures are present. Therefore, there is the need to teach students the whole range of embedded design - starting from the basics of computer architecture through to real chip design. In this paper, we present our experience with a holistic teaching approach in embedded multi-core computing, which covers most aspects of embedded system design. Beginning with the theoretical foundations of computer architecture, a custom multi-core CPU is designed by teams of students and finally transferred to a complete IC layout. As a distinctive feature, the layout is manufactured and packaged. The students will get their own processor chip, which they can test and evaluate. Student surveys show that the students are highly motivated to obtain the opportunity to produce their own chip. This results in active participation in the lessons/seminars and the training of valuable social skills.

Teaching heterogeneous computer architectures using smart camera systems

Although in recent years multi-core processors have left their academic niche and became more and more popular, the need for energy efficient and powerful devices could not been fulfilled completely. Therefore, the focus in research as well as in industry is nowadays drawn to new architecture concepts especially heterogeneous computing architectures. Unfortunately, the design and programming of these architectures is more complex than standard processing solutions. Hence, it is essential to teach current students, how the systems of tomorrow must be constructed and programmed. In this paper we are presenting our experience with a lab focusing on the design and programming of heterogeneous computing architectures for smart cameras. We have chosen this example since image processing systems can heavily benefit from heterogeneous architectures utilizing different architectural concepts for different image processing operators. Moreover, using smart camera applications from industry are a high motivation for students. Therefore, the course contains the implementation of a complete image processing application beginning from data acquisition of the sensor to image pre- and post-processing and finally to the usage of an embedded operating system for integrating the camera in real industrial scenarios. Our student evaluation show, that all participants were able to build a heterogeneous system and understand and evaluate the benefits of these architecture.

Fast image processing for optical metrology utilizing heterogeneous computer architectures

Display Omitted Image processing applications can benefit from heterogeneous computing architectures.Using FPGAs, GPUs and CPUs together enables a fast image processing pipeline.FPGA architectures within smart cameras can increase throughput and decrease latency.The image processing pipeline was demonstrated at the example of optical metrology. Industrial image processing tasks, especially in the domain of optical metrology, are becoming more and more complex. While in recent years standard PC components were sufficient to fulfill the requirements, special architectures have to be used to build high-speed image processing systems today. For example, for adaptive optical systems in large scale telescopes, the latency between capturing an image and steering the mirrors is critical for the quality of the resulting images. Commonly, the applied image processing algorithms consist of several tasks with different granularities and complexities. Therefore, we combined the advantages of multicore CPUs, GPUs, and FPGAs to build a heterogeneous image processing pipeline for adaptive optical systems by presenting new architectures and algorithms. Each architecture is well-suited to solve a particular task efficiently, which is proven by a detailed evaluation. With the developed pipeline it is possible to achieve a high throughput and to reduce the latency of the whole steering system significantly.

Framework for parameter analysis of FPGA-based image processing architectures

Image processing algorithms which only work on a local neighbourhood are nearly used in every image processing application. Very often several iterations are performed on a fixed neighbourhood which leads to the description of stencil codes. A promising approach in embedded systems is to use the massively parallel computation power of an FPGA for this kind of algorithms. This not only speeds up processing time, if the FPGA is directly placed inside the image acquisition unit forming a smart camera, but also reduces or even eliminates the PC based hardware which saves space and power. However, most designers begin from scratch when they have to implement stencil computations into smart cameras. This leads to a not fully utilized FPGA because the most efficient usage of the given resources is only secondary alongside functional correctness. Therefore, we are presenting in this paper a framework for stencil code applications which immediately delivers the best architecture regarding prominent resource criteria. An analytical model is used to find an optimized parameter set (degree of parallelism, usage of buffers, etc.) for a highly flexible FPGA implementation. A graphical tool allows to further evaluate the effects of certain parameters. Our results show, that we are able to create an optimized hardware architecture for this application domain.

Comprehensive curriculum for reconfigurable heterogeneous computer architecture education

As heterogeneity in desktop processor chips was recently promised by the major manufactures, the importance of these new architecture paradigms strongly grows. Especially if programmable CPUs are combined with reconfigurable logic like it has been done in the embedded domain, the complexity to design an energy efficient and powerful system increases. Therefore, heterogeneous system platforms have to be focused even stronger in research and education. Because the design and programming of these architectures is much more complex than using standard processor solutions, it is essential to provide thorough education programs for students. Only then will the engineers of tomorrow be able to deal with the future challenges. As a consequence, the authors restructured their curriculum to especially deal with the upcoming needs. Three courses were oriented towards the common goal of developing a real-world smart camera solution utilising heterogeneous architectures. The new combination provides various synergistic benefits and evaluation results confirm, that the overall orientation of the courses is a step in the right direction. As the basic components are already available at many other universities, their example can encourage to launch similar programmes elsewhere.

Smart Sensor Framework: A Pressure Sensor for Smart Home Applications

Smart home automation applications require a dense information network for proper func-tionality. Air-conditioning or filtration systems, for example, must detect airflows caused by openwindows and doors. An unambiguous detection of such airflows can be performed by a distributedsensor network. Current off-the-shelf sensors often lack processing and communication units, resulting in a large design assembly of discrete integrated circuits (ICs) on one printed circuit board (PCB)that requires additional power supply. Distributing such designs within a home without interferingwith the existing surroundings proves to be difficult in terms of acceptance and usability. This paperpresents a solution by offering an integrated design that includes a microelectromechanical system(MEMS) pressure sensor element along with an analog to digital converter (ADC) and a customizableand programmable processing unit. The integration leads to a smaller overall footprint and reducedpower consumption, which positively affects the acceptance rate of distributed smart sensor networksfor home automation. Clear interfaces between the components ensure an extensible and adaptablesystem design suitable for further smart sensor applications, resulting in a smart sensor framework.

Generic Emergent Computing in Chip Architectures

This article presents some implementations of architectures for emergent algorithms using Marching Pixels (MP). After a short presentation of recent work, we introduce application specific architectures for MP and their hardware implementations. An FPGA solution and an ASIC was made which allows to find the first and second moments of all objects by a specific MP algorithm in less than 10 ms for a megapixel resolution of a given image. In the second part we are presenting a fully programmable SIMD architecture (ParCA) for a fast processing of Cellular Automata (CA). It uses image partitioning with the help of double buffering and has an own assembler which allows an easy implementation of MP-algorithms. FPGA prototyping was accomplished and an ASIC with integrated SRAM and a DRAM Controller for external memory access were layouted. Our results show that easy morphological operations can be done with 390 fps and the implementation of the flooding algorithm is 40 times faster than an Intel Atom processor at 1.6 GHz.