Benoit Deschamps

A 2.2-

This paper presents the investigation of a 2.2-mum-pitch single-transistor pixel designed in a 0.13-mum CMOS process. Based on charge-induced potential variation of the floating-body of the transistor, this single pixel device can be operated to perform photodetection, charge integration, signal readout, and reset. The main electrical characteristics of the pixel are evaluated by device modeling and simulations as well as measurements of test chips. With optimization of process and electrical parameters, testing results show a conversion factor of 47 muV/hole, a charge-handling capability of 3500 holes, a temporal noise of four holes, and a dynamic range of 40 dB.

\mu\hbox{m}

This paper describes the implementation of a single-transistor (1T) charge-modulation pixel structure. It consists of a NMOS transistor with specific channel implant in a floating P-well. This same transistor can be operated for photosensing, charge storage, integration, readout and reset. A 2.2 mum pixel pitch array has been designed and fabricated in a 0.13 mum CMOS process. Testing results show a charge-voltage conversion factor of 35 muV/hole, and a charge storage capacity of 6200 holes without lag retention. They also confirm that the use of specific channel implant suppresses effectively Si/SiO2 interface trapping noise to achieve a temporal noise of 200 muV

-Pitch Single-Transistor Charge-Modulation Pixel in a 0.13-

We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

\mu\hbox{m}

To evaluate electrical characteristics of the 1T charge-modulation pixel, we propose two design configurations: one is a 2.2μm-pitch, rectangular-gate pixel, and the other is a 1.4μm-pitch, ring-gate pixel. The former allows the transistor size to be minimized, but requires surrounding STI (Shallow Trench Isolation) to reduce electrical crosstalk. The latter is advantageous in terms of pixel size and fill factor, mainly thanks to STI suppression. The two design configurations are respectively integrated in test chips. Our measured results confirm the scaling law: reducing pixel size improves conversion gain, but degrades full well capacity (FWC). They also show that dark current of the 1.4μm-pitch ring-gate pixel is much lower than the 2.2μm-pitch rectangular-gate counterpart. This low dark current achievement may be explained by: i) suppression of STI-induced surface leakage current component, ii) smooth-shape layout to minimize band-to-band tunneling effect, and iii) smaller pixel size with smaller depletion areas which has, accordingly, lower thermally-generated dark current components. The 1.4μm-pitch ring-gate pixel also has lower noise, especially much lower dark FPN. This seems to confirm that dark FPN may have a large contribution from dark current generation. The dynamic range for the 1.4μm-pitch pixel is larger, meaning that signal-to-noise ratio outweighs FWC degradation. However, the sensitivity, like FWC, is also degraded in the same proportion. There are possibilities of improvements especially by process optimization.