Berna Ors

Hardware implementation of an elliptic curve processor over GF(p) with Montgomery modular multiplier

This paper describes a hardware implementation of an arithmetic processor which is efficient for bit-lengths suitable for both commonly used types of Public Key Cryptography, i.e., Elliptic Curve (EC) and RSA Cryptosystems. Montgomery modular multiplication in a systolic array architecture is used for modular multiplication. The processor consists of special operational blocks for Montgomery modular multiplication, modular addition/subtraction, EC Point doubling/addition, modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversion and Montgomery to normal representation conversion.

Design of new tiny circuits for AES encryption algorithm

Advanced Encryption Standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.

Differential power analysis attack considering decoupling capacitance effect

We examine the differential power analysis attack (DPA) on a pipelined FPGA implementation of AES when decoupling capacitors are in the circuit. In a recent work, researchers pointed out the use of the decoupling capacitors is inevitable for the encryption hardware operating at high clock frequencies. Also, use of the decoupling capacitance is advisable to protect the cryptographic algorithms against DPA attack since current is going to be delivered from the closest capacitor, not from the power supply. In this work we show that decoupling capacitors are not a protection method against DPA attack. In contrast, they are the local source for the charge delivery at high frequencies. Being able to observe the current flow on the pin renders the circuit open for attacks. As a result, integrated circuits (IC) working at high frequency range are still vulnerable to attack. We define the frequencies at which attack is successful. Our work gives the results when we attack on AES implementation by observing decoupling capacitor current flow of an FPGA operating up to 66 MHz clock frequency.

Differential Power Analysis resistant hardware implementation of the RSA cryptosystem

In this paper, RSA cryptosystem was implemented on an FPGA as resistant against differential power analysis attacks. There are hardware and algorithmic countermeasures against power analysis attacks. This is the first FPGA realization of an algorithmic countermeasure which makes RSA resistant to power analysis attacks. Modular exponentiation is realized with Montgomery modular multiplication. The Montgomery modular multiplier has been realized with carry save adders. Carry save representation has been used throughout the RSA encryption algorithm. The protected implementation resulted in 66,66 MHz of clock frequency, 84,42 Kb/s of throughput, and 6,06 ms of total exponentiation time and occupied an area of 10986 slices with the use of the built-in block SelectRAM structure inside XCV1000E.

Power Analysis Resistant Hardware Implementations of AES

This paper presents the first FPGA implementation of the Advanced Encryption Standard (AES) with masking countermeasure for the power analysis (PA) attacks. PA is a powerful side-channel analysis (SCA) attack. A side-channel analysis (SCA) attack takes advantage of implementation specific characteristics to recover the secret parameters involved in the computation. The goals of side-channel attack countermeasures are reducing the correlation between the side-channel data and the secret data. Data masking is one of the most powerful countermeasure against side channel attacks. The message and the key are masked with some random values at the beginning of computations. We have implemented the AES algorithm on an FPGA by using two different masking method: multiplicative and additive.

IoT in Action

With the development of sensor technologies, various application areas have emerged. The usage of these technologies and exploitation of recent improvements have clear benefits on building applications. Such use-cases can improve smart functions of buildings and can increase the end-user comfort. As a similar notion, building automation systems (BAS) are smart systems that target to provide automated management of various control services and to improve resource usage efficiency. However, buildings generally contain hardware and control services from a diverse set of characteristics. The automated and central management of such functions can be challenging. In order to overcome such issues, an Emergency Evacuation Service is proposed for BAS, where requirements of such central management model are analyzed and model content and subservice definitions are prepared. A crucial scenario, which could be a necessity for future BAS, is defined and an approach for evacuation of people in the buildings at emergency situations is proposed. For real-life scenarios, the Evacuation Service is implemented by using a low-cost design, which is appropriate for Internet of Things (IoT) based BAS applications. As demonstrated, the proposed service model can provide effective performance in real-life deployments.

Hardware/Software codesign for watermarking in DCT domain

Digital images are used in many areas. Because of that, digital image watermarking has become an important research topic by the view of protecting copyright. Several methods have being developed to protect the watermarking on the image from additional processes. DCT is one of the methods used for robustness of watermarking. In this work, Hardware/Software co-design image watermarking system is designed with using DCT on FPGA. Thus, transform operations are made faster via hardware. Watermarking method is made changeable easily with software.

Reliability and security of arbiter‐based physical unclonable function circuits

SUMMARY Physical unclonable functions (PUFs) are considered as a promising technology that would be used for secure key generation and storage, integrated circuit (IC) authentication, and chip-unique signature generation. On the basis of the delay variation of logic gates across ICs, PUF circuits could be used to generate secret keys attached to some challenge–response schemes. In this study, an arbiter-based PUF circuit is implemented on Xilinx Virtex 2 Pro field-programmable gate array (Xilinx, Inc., San Jose, CA, USA), and its identification capability, reliability, and security are investigated. For this purpose, we define and measure the parameters such as interchip variation and environmental noise, which are important in the identification process of different ICs. In order to test the resistance of PUF circuit against software attacks, we applied two approaches. In the first one, we use a support vector machine classifier, and attacks are considered as a classification problem. In the second one, linear programming technique is applied to find the delay variables corresponding to the linear model of the PUF circuit.Copyright

Architectures for Fast Modular Multiplication

Modular multiplication is the key ingredient needed to realize most public-key cryptographic primitives. In a modular setting, multiplications are carried in two steps: namely a usual integer arithmetic followed by a reduction step. Progress in any of these steps naturally improves the modular multiplication but it is not possible to interleave the best algorithms of these stages. In this study, we propose architectures for recently proposed method of interleaving the Karatsuba-Ofman multiplier and bipartite modular reduction on the upper most layer of Karatsuba-Ofmans recursion. We manage to come up with a high performance modular multiplication architecture by taking the advantage of a fast multiplication and a parallel reduction method.

Design and implementation of a custom verification environment for fault injection and analysis on an embedded microprocessor

Embedded microprocessors are widely used in most of the safety critical digital system applications. A fault in a single bit in the microprocessors may cause soft errors. It has different affects on the program outcome whether the fault changes a situation in the application. In order to analyse the behaviour of the applications under the faulty conditions we have designed a custom verification system. The verification system has two parts as Field Programmable Gate Array (FPGA) and personnel computer (PC). We have modified Natalius open source microprocessor in order to inject stuck-at-faults into it. We have handled a fault injection method and leveraged it to increase randomness. On FPGA, we have implemented modified Natalius microprocessor, the fault injection method and the communication protocol. Then the “Most Significant Bit First Multiplication Algorithm” has been implemented on the microprocessor as an application. We have prepared an environment which sends inputs to and gets outputs from the Natalius microprocessor on PC part. Finally, we have analysed our application by injecting faults in specific location and random location in register file to make some classifications for effects of the injected faults.