Bernhard Wicht

MHz-converter design for high conversion ratio

This paper presents a circuit design and efficiency study for integrated converters with switching frequencies up to 15 MHz at high conversion ratio with input voltages up to 40 V and output voltages <;5 V. An asynchronous buck converter is well suitable, while in contrast, a synchronous topology causes larger switching losses due to its low side switch. Critical design aspects are presented along with an implementation in a 180 nm HV BiCMOS technology. A saw-tooth with fast fall time is achieved with two interleaved integrator stages. The limitation due to the finite fall-time of the saw tooth signal was solved by a PWM comparator that gets reset by a synchronized clock with an adjusted lead time at min. or max. duty cycle, respectively. A high speed level shifter is used to shift the PWM signal to the high side domain. The gate driver uses a two-branch tapered buffer with asymmetry factor to achieve maximum switching speed while at the same time the current consumption is minimized. An efficiency model, verified by measurements, allows to simulate and to determine quantitatively the root cause of the power losses separately for each circuit block. At 15 MHz and 10 V input voltage a peak efficiency of ~65% was achieved. While the efficiency reduces to about 35% for a conversion from 40 V input to 5 V output, resonant concepts are expected to reach >50% efficiency. In experiments a switching frequency of 40 MHz was achieved.

A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters

Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum input voltage range, respectively, is limited by the minimum propagated on-time pulse, which is mainly determined by the level shifter speed. At switching frequencies above 10 MHz, a voltage conversion with an input voltage range up to 50 V and output voltages below 5 V requires an on-time of a pulse width modulated signal of less than 5 ns. This cannot be achieved with conventional level shifters. This paper presents a level shifter circuit, which controls an NMOS power FET on a high-voltage domain up to 50 V. The level shifter was implemented as part of a DCDC converter in a 180 nm BiCMOS technology. Experimental results confirm a propagation delay of 5 ns and on-time pulses of less than 3 ns. An overlapping clamping structure with low parasitic capacitances in combination with a high-speed comparator makes the level shifter also very robust against large coupling currents during high-side transitions as fast as 20 V/ns, verified by measurements. Due to the high dv/dt, capacitive coupling currents can be two orders of magnitude larger than the actual signal current. Depending on the conversion ratio, the presented level shifter enables an increase of the switching frequency for multi-MHz converters towards 100 MHz. It supports high input voltages up to 50 V and it can be applied also to other high-speed applications.

EMC Optimized Design of Linear Regulators Including a Charge Pump

The charge pump belongs to the most critical blocks for electromagnetic compatibility (EMC) of low dropout linear regulators (LDO) because of its switching nature. The goal of this paper is to contribute charge pump design practice and a prediction method for the LDO EMC performance already in an early design phase. LDO noise coupling mechanisms are analyzed. EMC aware circuit design includes the choice of low-noise architectures, the right switching frequency, and noise filtering. The derived simulation method shows very good matching with EMC test results for an LDO with two different charge pumps fabricated in 350 nm high-voltage BiCMOS technology. For a realistic prediction of the EMC noise magnitude, a relative simple simulation setup gives results with less than 3 dB μV accuracy. A tripler current mode charge pump turned out to be well suitable for EMC. Conducted emissions could be predicted and confirmed to be improved by ~50 dBμV versus a conventional voltage-mode charge pump.

Bootstrap circuit with high-voltage charge storing for area efficient gate drivers in power management systems

Bootstrap circuits are mainly used for supplying a gate driver circuit to provide the gate overdrive voltage for a high-side NMOS transistor. The required charge has to be provided by a bootstrap capacitor which is often too large for integration if an acceptable voltage dip at the capacitor has to be guaranteed. Three options of an area efficient bootstrap circuit for a high side driver with an output stage of two NMOS transistors are proposed. The key idea is that the main bootstrap capacitor is supported by a second bootstrap capacitor, which is charged to a higher voltage and connected when the gate driver turns on. A high voltage swing at the second capacitor leads to a high charge allocation. Both bootstrap capacitors require up to 70% less area compared to a conventional bootstrap circuit. This enables compact power management systems with fewer discrete components and smaller die size. A calculation guideline for optimum bootstrap capacitor sizing is given. The circuit was manufactured in a 180nm high-voltage BiCMOS technology as part of a high-voltage gate driver. Measurements confirm the benefit of high-voltage charge storing. The fully integrated bootstrap circuit including two stacked 75.8pF and 18.9pF capacitors results in a voltage dip lower than 1V. This matches well with the theory of the calculation guideline.

12.4 A 10mW fully integrated 2-to-13V-input buck-boost SC converter with 81.5% peak efficiency

In recent years, significant progress has been made on switched-capacitor DC-DC converters as they enable fully integrated on-chip power management. New converter topologies overcame the fixed input-to-output voltage limitation and achieved high efficiency at high power densities [1-6]. SC converters are attractive to not only mobile handheld devices with small input and output voltages, but also for power conversion in IoE, industrial and automotive applications, etc. Such applications need to be capable of handling widely varying input voltages of more than 10V, which requires a large amount of conversion ratios [1-3]. The goal is to achieve a fine granularity with the least number of flying capacitors. In [1] an SC converter was introduced that achieves these goals at low input voltage VIN ≤ 2.5V. [2] shows good efficiency up to VIN = 8V while its conversion ratio is restricted to ≤1/2 with a limited, non-equidistant number of conversion steps. A particular challenge arises with increasing input voltage as several loss mechanisms like parasitic bottom-plate losses and gate-charge losses of high-voltage transistors become of significant influence. High input voltages require supporting circuits like level shifters, auxiliary supply rails etc., which allocate additional area and add losses [2-5]. The combination of both increasing voltage and conversion ratios (VCR) lowers the efficiency and the achievable output power of SC converters. [3] and [5] use external capacitors to enable higher output power, especially for higher VIN. However, this is contradictory to the goal of a fully integrated power supply.

An 18 V Input 10 MHz Buck Converter With 125 ps Mixed-Signal Dead Time Control

A highly integrated synchronous buck converter with a predictive dead time control for input voltages >18 V with 10 MHz switching frequency is presented. A high resolution dead time of ~125 ps allows to reduce dead time dependent losses without requiring body diode conduction to evaluate the dead time. High resolution is achieved by frequency compensated sampling of the switching node and by an 8 bit differential delay chain. Dead time parameters are derived in a comprehensive study of dead time depended losses. This way, the efficiency of fast switching DC-DC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching. High-speed circuit blocks for fast switching operation are presented including level shifter, gate driver, PWM generator. The converter has been implemented in a 180 nm high-voltage BiCMOS technology. The power losses were measured to be reduced by up to 31% by the proposed dead time control, which results in a 5.3% efficiency increase at VIN =18 V, VOUT =5 V, and 0.45 A load. At VIN =12 V, the peak efficiency is 81.2% with an efficiency improvement of 6% with dead time control.

A 20 V, 8 MHz resonant DCDC converter with predictive control for 1 ns resolution soft-switching

Fast switching power supplies allow to reduce the size and cost of external passive components. However, the capacitive switching losses of the power stage will increase and become the dominant part of the total losses. Therefore, resonant topologies are the known key to reduce the losses of the power stage. A power switch with an additional resonant circuit can be turned on under soft-switching conditions, ideally with zero-voltage-switching (ZVS). As conventional resonant converts are only efficient for a constant load, this paper presents a predictive regulation loop to approach soft-switching conditions under varying load and component tolerances. A sample and hold based detection circuit is utilized to control the turn-on of the power switch by a digital regulation. The proposed design was fabricated in a 180 nm high-voltage BiCMOS technology. The efficiency of the converter was measured to be increased by up to 16 % vs. worst case timing and by 13 % compared to a conventional hard-switching buck converter at 20 V input voltage and at approximately 8 MHz switching frequency.

Isolated 100% PWM gate driver with auxiliary energy and bidirectional FM/AM signal transmission via single transformer

Galvanic isolated gate drivers require a control signal as well as energy transmission from the control side (low-side) to the driver side (high-side). An additional backward signal transmission is preferred for error signals, status information, etc. This is often realized by means of several transformers or opto-couplers. Decreasing the number of isolation elements results in lower cost and a higher degree of miniaturization. This work presents a gate driver with bidirectional signal transmission and energy transfer via one single transformer. The key concept proposed in this paper is to combine bootstrapping to deliver the main gate charge for the driven power switch with additional energy transfer via the signal transformer. This paper also presents a very efficient combination of energy transfer to two high-side supply rails with back channel amplitude modulation. This way an isolated gate driver can be implemented that allows 100% pulse-width modulation (PWM) duty cycle at low complexity and system cost. The proposed high-side driver IC with integrated power supply, modulation and demodulation circuits was manufactured in a 180nm high-voltage BiCMOS technology. Measurements confirm the concept of bidirectional signal transmission with a 1MBit/s amplitude modulation, 10/20MHz frequency modulation and a maximum power transmission of 14mW via the transformer.

A 10 MHz, 48-to-5V synchronous converter with dead time enabled 125 ps resolution zero-voltage switching

An integrated synchronous buck converter with a high resolution dead time control for input voltages up to 48V and 10MHz switching frequency is presented. The benefit of an enhanced dead time control at light loads to enable zero voltage switching at both the high-side and low-side switch at low output load is studied. This way, compact multi-MHz DCDC converters can be implemented at high efficiency over a wide load current range. The concept also eliminates body diode forward conduction losses and minimizes reverse recovery losses. A dead time resolution of 125 ps is realized by an 8-bit differential delay chain. A further efficiency enhancement by soft switching at the high-side switch at light load is achieved with a voltage boost of the switching node by dead time control in forced continuous conduction mode. The monolithic converter is implemented in an 180nm high-voltage BiCMOS technology. At VIN = 48V, VOUT = 5V, 50mA load, 10MHz switching frequency and 500 nH output inductance, the efficiency is measured to be increased by 14.4% compared to a conventional predictive dead time control. A peak efficiency of 80.9% is achieved at 12V input.

Area Efficient Integrated Gate Drivers Based on High-Voltage Charge Storing

For area reasons, NMOS transistors are preferred over PMOS for the pull-up path in gate drivers. Bootstrapping has to ensure sufficient NMOS gate overdrive. Especially in high-current gate drivers with large transistors, the bootstrap capacitor is too large for integration. This paper proposes three options of fully integrated bootstrap circuits. The key idea is that the main bootstrap capacitor is supported by a second bootstrap capacitor, which is charged to a higher voltage and ensures high charge allocation when the driver turns on. A capacitor sizing guideline and the overall driver implementation including a suitable charge pump for permanent driver activation is provided. A linear regulator is used for bootstrap supply and it also compensates the voltage drop of the bootstrap diode. Measurements from a testchip in 180 nm high-voltage BiCMOS confirm the benefit of high-voltage charge storing. The fully integrated bootstrap circuit with two stacked 75.8 pF and 18.9 pF capacitors results in an expected voltage dip of lower than 1 V. Both bootstrap capacitors require 70% less area compared to a conventional bootstrap circuit. Besides drivers, the proposed bootstrap can also be directly applied to power stages to achieve fully integrated switched mode power supplies or class-D output stages.