Bertrand Szelag

High-Performance 15-V Novel LDMOS Transistor Architecture in a 0.25-

The optimization of the small and large signal performances of a radio frequency (RF)-LDMOS is presented via the achievement of a novel LDMOS architecture. Specific process steps are introduced into a 0.25-mum BiCMOS technology and precisely described to realize a fully salicided gate RF-LDMOS architecture. Significant improvement is obtained on the small-signal - fT and Fmax - and power performances while maintaining good dc characteristics

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An optimized LDMOSFET and a SiGe:C HBT for PA design, integrated in a BiCMOS technology, are described in this article. Each device of interest, for PA applications, is highlighted via its electrical performance - static, small and large signal.

BiCMOS Process for RF-Power Applications

In this paper, we present the optimisation of a RF lateral DMOS and its integration in an advanced 0.25 /spl mu/m SiGe:C BiCMOS technology. The proposed device shows excellent characteristics; Ron is around 2.5 /spl Omega/.mm with a BVDS larger than 13 V, f/sub T/ and F/sub max/ reach 21 GHz and 40 GHz respectively. These performances fit wireless RF-power amplifier needs. Integration of such a device in a RF oriented BiCMOS process is a key issue for a SOC approach of wireless circuits.

LDMOSFET and SiGe:C HBT integrated in a 0.25 /spl mu/m BiCMOS technology for RF-PA applications

The improvement of the dynamic performances of a RF LDMOS power amplifier (PA) is presented via the investigation of two device architectures differently optimized: LDMOSo1 and LDMOSo2. The diminution of the capacitance Cds was achieved on LDMOSo1. The reduction of key parameters such as the gate resistance Rg, and the capacitance Cgd was obtained on LDMOSo2. Both optimized architectures could be combined to gain on dynamic performances and complete the LDMOSFET optimization.

Integration and optimisation of a high performance RF lateral DMOS in an advanced BiCMOS technology

LDMOSFET optimization for RF power applications is discussed. Starting from a quite standard transistor, a new architecture has been developed to reach high RF performances without sacrificing DC characteristics. The parasitic elements affecting the RF performances have been identified and reduced. The optimized device presents the following performances: BVds=15V, W.Ron lower than 3 Ohm.mm and f/sub T/ larger than 30 GHz.

Architecture optimization of an N-channel LDMOS device dedicated to RF-power application

Integration of RF power amplifier in silicon technology is a new challenge. RF lateral DMOS is one of the main candidates to achieve this objective. In this paper, the integration and optimization of an alternative RF N-type lateral DMOSFET in an advanced 0.25/spl mu/m RF BiCMOS technology are presented. The main optimization steps on DC and RF parameters are described. Linear characteristics and dynamic performances achieved are equivalent to the standard LDMOS architecture.

NLDMOS RF optimization guidelines for wireless power amplifier applications

This paper describes a WCDMA direct conversion receiver which has been integrated in a BiCMOS SiGe-carbon process featuring 0.25 /spl mu/m/f/sub T/=60 GHz bipolar transistors. This receiver includes an integrated RF-front-end with local oscillator quadrature generator, 5/sup th/ order Butterworth analog baseband lowpass filter (LPF) and variable gain amplifier (VGA), cut-off frequency calibrator, DAC for DC-offset calibration, serial bus interface and voltage and current reference generators. In the high/low gain modes, this device consumes 25 mA and 20 mA respectively with 2.7 V power supply. The die is wire bonded directly on the validation board. Within the receive band, the measurements show 51 dB of overall gain, NF=5 dB, IIP3= -9 dBm, ICP1 = -15dBm.

Comparison of two types of lateral DMOSFET optimized for RF power applications

Germanium photodetectors are considered to be mature components in the silicon photonics device library. They are critical for applications in sensing, communications, or optical interconnects. In this work, we report on design, fabrication, and experimental demonstration of an integrated waveguide PIN photodiode architecture that calls upon lateral double Silicon/Germanium/Silicon (Si/Ge/Si) heterojunctions. This photodiode configuration takes advantage of the compatibility with contact process steps of silicon modulators, yielding reduced fabrication complexity for transmitters and offering high-performance optical characteristics, viable for high-speed and efficient operation near 1.55 μm wavelengths. More specifically, we experimentally obtained at a reverse voltage of 1V a dark current lower than 10 nA, a responsivity higher than 1.1 A/W, and a 3 dB opto-electrical cut-off frequency over 50 GHz. The combined benefits of decreased process complexity and high-performance device operation pave the way towards attractive integration strategies to deploy cost-effective photonic transceivers on silicon-on-insulator substrates.

Fully-integrated WCDMA direct conversion SiGeC BiCMOS receiver

Silicon photonics is of great interest as it opens the way to large bandwidth and high data rates. A pioneer Silicon photonics scheme consists in integrating III-V lasers on the SOI substrates containing the passive components. However, key developments are necessary to co-integrate III-V devices with CMOS very large scale integration (VLSI). In this paper we propose a CMOS-compatible integration scheme of contacts (i.e. semiconductor metallization and plug) on III-V surfaces taking into account the limitations fixed by the operating laser device. Based on metallurgical, morphological, optical and electrical studies, processes are submitted and reviewed for the purpose of forming stable and reproducible contacts with low resistivity in a 200 millimeters fab line.

Integrated waveguide PIN photodiodes exploiting lateral Si/Ge/Si heterojunction

Optical switches based on ring resonator cavities were fabricated by a silicon photonics foundry process and analyzed for optical crosstalk at various data rates and channel spacings. These devices were compared to commercial bandpass filters and at 20Gb/s, 0.5dB power penalty is observed due to spectral filtering for bit error ratio threshold of 1 × 10-9. Concurrent modulation at 20Gb/s with a channel spacing as narrow as 40GHz shows error-free transmission with 1dB power penalty as compared to wider channel spacing for the ring-based switch.