Bertrand Vrignon

Modeling the Electromagnetic Emission of a Microcontroller Using a Single Model

This paper presents a methodology for building an integrated circuit behavioral model that enables the prediction of its electromagnetic (EM) emissions up to several gigahertz. The model, built upon S-parameter characterization and conducted emission measurements, is used to predict the EM emissions of a commercial 16-bit microcontroller. The emission measurements are performed according to several EM compatibility standards, namely, 1 Omega /150 Omega , surface scan, and transverse EM/gigahertz transverse EM (GTEM) method, and their results show an excellent fit with model predictions.

Characterization and modeling of parasitic emission in deep submicron CMOS

This paper presents a study of the parasitic emissions of a 0.18-/spl mu/m CMOS experimental integrated circuit (IC) and an accurate method for modeling the internal current switching to forecast electromagnetic interference (EMI). The effectiveness of emission reduction techniques is quantified through a set of conducted noise measurements. A simple core model is developed, based on the current switching activity. Added to a lumped-element model of the test board and the package, good agreement between simulation and measurements are obtained up to 10 GHz. The simulation methodology may be applied to forecast the impact of low emission design techniques on the EMI of ICs.

On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations

With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of noncompliance becomes critical for circuit designers. However, an on-chip characterization of noise is still necessary for model validation and design optimization. Although different on-chip measurement solutions have been proposed for emission issue characterization, no on-chip measurement methods have been proposed to address the susceptibility issues. This paper presents an on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences. A demonstration of the sensor measurement performances and benefits is proposed through a study of the susceptibility of a digital core to conducted interferences. Sensor measurements ensure a better characterization of actual coupling of interferences within the circuit and a diagnosis of failure origins.

Characterization of the Evolution of IC Emissions After Accelerated Aging

With the evolving technological development of integrated circuits, ensuring electromagnetic compatibility (EMC) is becoming a serious challenge for electronic circuit and system manufacturers. Although electronic components must pass a set of EMC tests to ensure safe operations, the evolution of EMC over time is not characterized and cannot be accurately forecast. This paper presents an original study about the consequences of the aging of circuits on electromagnetic emissions. Different types of standard applicative and accelerated life tests are applied on a mixed power circuit dedicated to automotive applications. Its conducted emissions are measured before and after these tests, showing variations in EMC performance. Comparisons between each type of aging procedure show that the emission level of the circuit under test is differently affected.

Modeling and Simulation of LDO Voltage Regulator Susceptibility to Conducted EMI

This paper presents a methodology dedicated to modeling and simulation of low-dropout (LDO) voltage regulator susceptibility to conducted electromagnetic interference (EMI). A test chip with a simple LDO structure was designed for EMC test and analysis. A transistor-level model, validated by functional tests, Z-parameter characterization and direct power injection (DPI) measurements, is used to predict the immunity of the LDO regulator. Different levels of model extraction reveal the weight contributions of subcircuits and parasitic elements on immunity issues. The DPI measurement results show a good fit with model prediction up to 1 GHz.

Prediction of aging impact on electromagnetic susceptibility of an operational amplifier

This paper deals with the impact of aging on the electromagnetic susceptibility level of a CMOS operational amplifier (opamp). The aging impact can be modelled by the variation of several parameters of the MOSFET model, to predict the evolution of electromagnetic susceptibility (EMS) of the opamp block during the aging process.

Prediction of long-term immunity of a phase-locked loop

Degradation mechanisms accelerated by harsh conditions (high temperature, electrical stress) can affect circuit performances. Submitted to electromagnetic interferences, aged components can become more susceptible, which stirs up questions about the safety level of the final application. Unfortunately, the impact of circuit aging on its susceptibility level remains under evaluated and is not taken into account at circuit design level. This paper presents a first attempt of a modeling methodology aiming at predicting the impact of circuit aging on the susceptibility to electromagnetic interferences. This methodology is applied to model and explain the measured variation of the susceptibility level of phase-locked loop after an accelerated-life test.

On-chip sampling and EMC modeling of I/Os switching to evaluate conducted RF disturbances propagation

This paper deals with the propagation of RF disturbances injected inside an integrated circuit. To increase our knowledge about this topic, an on-chip voltage sensor is implemented inside a test vehicle to quantify the conducted RF disturbances injected on the power supply of its I/Os. The experiment results give information about coupling paths taken by conducted disturbances carried into I/Os. I/O immunity thresholds computed from standard external immunity tests (IEC 62132-4) are compared to the one deduced from internal measurements. Moreover, in view of developing simulation tools for ICs immunity prediction, a test vehicle model is proposed. Comparison between simulation results, internal and external measurements raises some discussions about the accuracy of immunity measurement set-ups.

Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI)

Electromagnetic fault injections are produced on secured ICs aiming to break crypto codes. We describe in this paper the whole chain of optimization necessary to achieve this goal, namely 1/ physical optimization of near-field probe and setup, 2/ signal management in timing, shape, and localization to induce the fault while beating countermeasures and 3/ understanding of fault propagation in logic to eventually protect future ICs.

Characterizing integrated circuit susceptibility with on-chip sensors

With the growing concerns about susceptibility of integrated circuits to electromagnetic interferences, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. However, on-chip characterization of noise is still necessary for model validation. This paper presents an on-chip noise sensor dedicated to the time-domain measurement of voltage fluctuations and failures induced by electromagnetic interference coupling.